Abstract
This paper presents source degenerated cascode 60 GHz Low Noise Amplifier (LNA) is modelled in ADS and its performance is measured by computing Noise Figure (NF) and gain from simulation waveforms. Parameters such as LNA linearity and stability is determined and designed to be within permissible limits. The designed LNA is optimized for its area with 30% reduction. The measured result of the designed LNA shows 19.48 dB gain, 4.7 dB NF and IIP3 of –10 dBm. The Figure of Merit (FoM) characterized as an element of the NF and IIP3 is 17, which is the best outcome among past LNAs.
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References
Byeon, C.W., Yoon, C.H., Park, C.S.: A 67-mW 10.7-Gb/s 60-GHz OOK CMOS transceiver for short-range wireless communications. IEEE Trans. Microw. Theory Techn. 61(9), 3391–3401 (2013)
Okada, K., et al.: A full 4-channel 6.3 Gb/s 60 GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. In: IEEE ISSCC Digest of Technical Papers, pp. 218–220 (2012)
Razavi, B.: Design of millimeter-wave CMOS radios: a tutorial. IEEE Trans. Circuits Syst. I, Reg. Papers 56(1), 4–16 (2009)
Valdes-Garcia, A., et al.: A fully integrated 16-element phased-array transmitter in SiGe BiCMOS for 60-GHz communications. IEEE J. Solid-State Circuits 45(12), 2757–2773 (2010)
Yao, T., et al.: Algorithmic design of CMOS LNAs and PAs for 60-GHz radio. IEEE J. Solid-State Circuits 42(5), 1044–1057 (2007)
Gordon, M.Q., Yao, T., Voinigescu, S.P.: 65-GHz receiver in SiGeBiCMOS using monolithic inductors and transformers. In: Si Monolithic Integrated Circuits in RF Systems, pp. 265–268 (2007)
Floyd, B.A., et al.: SiGe bipolar transceiver circuits operating at 60 GHz. IEEE J. Solid State Circuits 40(1), 156–167 (2005)
Alldred, D., Cousins, B., Voinigescu, S.P., Rogers, E.S.: A 1.2 V, 60-GHz radio receiver with on-chip transformers and inductors in 90-nm CMOS. In: IEEE Compound Semiconductor Integrated Circuit Symposium, pp. 51–54 (2006)
Doan, C.H., Emami, S., Niknejad, A.M., Brodersen, R.W.: Millimeter-wave CMOS design. IEEE J. Solid-State Circuits 40(1), 144–155 (2005)
Razavi, B.: A 60-GHz direct-conversion CMOS receiver. In: IEEE International Solid-State Circuits Conference. Digest Technical Papers, vol. 1, pp. 400–606 (2005)
Heydari, B., Bohsali, M., Adabi, E., Niknejad, A.M.: Low-power mm-wave components up to 104 GHz in 90 nm CMOS. In: IEEE International Solid-State Circuits Conference (ISSCC) Digest Technical Papers, pp. 200–597 (2007)
Chikkanagouda, R., Cyril Prasanna Raj, P.: Design of cascode LNA with inductive source degeneration for 60 GHz applications. In: International Conference on Materials, Applied Physics and Engineering (ICMAE), Indore (2018)
Tsai, M.-H., et al.: Design of 60-GHz low-noise amplifiers with low NF and robust ESD protection in 65-nm CMOS. IEEE Trans. Microw. Theory Tech. 61(1), 553–561 (2013)
Hsieh, H.-H., et al.: 60 GHz High-Gain Low-Noise Amplifiers with a Common-Gate Inductive Feedback in 65 nm CMOS. In: IEEE Radio Frequency Integrated Circuits Symposium, pp. 1–4 (2011)
Fanaro, M., Olakede, S.S., Sinha, S.: Investigation of 60 GHz LNA with estimated S11 values based on mathematical model and numerical solution. Rom. J. Inf. Sci. Technol. 19(3), 239–254 (2016)
Liang, C.K., Razavi, B.: Systematic transistor and inductor modeling for millimeter-wave design. IEEE J. Solid-State Circuits 44(2), 450–457 (2009)
Dickson, T.O., et al.: The invariance of characteristic current densities in nanoscale MOSFETs and its impact on algorithmic design methodologies and design porting of Si(Ge) (Bi)CMOS high-speed building blocks. IEEE J. Solid-State Circuits 41(1), 1830–1845 (2006)
Niknejad, A.M.: MOSFET LNA Design. University of California, Berkeley (2005). http://rfic.eecs.berkeley.edu/~niknejad/ee142_fa05lects/pdf/lect14.pdf
Voinigescu, S.P., et al.: RF and millimeter-wave IC design in the nano-(Bi)CMOS era. Si-Based Semiconductor Components for Radio-Frequency Integrated Circuits (RFIC) (2006)
Predictive Technology Model, Latest Models. http://ptm.asu.edu/modelcard/2006/65nm_bulk.pm
International Technology Roadmap for Semiconductors (ITRS), 2005 Edn. (2005). https://www.semiconductors.org/clientuploads/Research_Technology/ITRS/2005/1_Executive%20Summary.pdf
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Chikkanagouda, R., Cyril Prasanna Raj, P. (2019). 60 GHz LNA Design with Inductive Source Degeneration in 65 nm CMOS Technology. In: Hemanth, J., Fernando, X., Lafata, P., Baig, Z. (eds) International Conference on Intelligent Data Communication Technologies and Internet of Things (ICICI) 2018. ICICI 2018. Lecture Notes on Data Engineering and Communications Technologies, vol 26. Springer, Cham. https://doi.org/10.1007/978-3-030-03146-6_40
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DOI: https://doi.org/10.1007/978-3-030-03146-6_40
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