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A 24-GHz power amplifier with Psat of 15.9 dBm and PAE of 14.6 % using standard 0.18 μm CMOS technology

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Abstract

A 24 GHz power amplifier for direct-conversion transceiver using standard 0.18 μm CMOS technology is reported. The three-stage power amplifier comprises two cascaded cascode stages for high power gain, followed by a common-source stage for high power linearity. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a Wilkinson-power-divider- and combiner-based two-way power dividing and combining architecture. The power amplifier consumes 163.8 mW and achieves power gain (S21) of 22.8 dB at 24 GHz. The corresponding 3-dB bandwidth of S21 is 4.2 GHz, from 22.7 to 26.9 GHz. At 24 GHz, the power amplifier achieves Psat of 15.9 dBm and maximum PAE of 14.6 %, an excellent result for a 24 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1dB) is 7 dBm at 24 GHz. These results demonstrate the proposed power amplifier architecture is very promising for 24 GHz short-range communication system applications.

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Acknowledgments

This work is supported by the National Science Council of the R.O.C. under Contracts NSC100- 222-E-260-011-MY3 and NSC100-2221-E-260-006-MY2. The authors are also very grateful for the support from National Chip Implementation Center (CIC), Taiwan, for chip fabrication, and National Nano-Device Laboratory (NDL), Taiwan, for high-frequency measurements.

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  1. Department of Electrical Engineering, National Chi Nan University, Puli, Taiwan, ROC

    Yo-Sheng Lin & Jing-Ning Chang

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  1. Yo-Sheng Lin
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  2. Jing-Ning Chang
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Correspondence to Yo-Sheng Lin.

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Lin, YS., Chang, JN. A 24-GHz power amplifier with Psat of 15.9 dBm and PAE of 14.6 % using standard 0.18 μm CMOS technology. Analog Integr Circ Sig Process 79, 427–435 (2014). https://doi.org/10.1007/s10470-014-0290-4

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  • DOI: https://doi.org/10.1007/s10470-014-0290-4

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