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Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

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Abstract

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S 21) of 14.5 dB, input P1dB of −17.5 dBm, and input IP3 of −13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S 21) of 17 dB, input P1dB of −22 dBm, and input IP3 of −14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure

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Notes

  1. In (15), (20), and (21) “l.ch.” denotes “long channel”.

  2. Since (29) and (30) are approximate, in the case when C ex ≈0, the two expressions may not be exactly consistent. In this case (29) should be used.

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Acknowledgement

This work was supported by The Natural Sciences and Engineering Research Council of Canada, The Alberta Provincial Government’s iCORE program, The National Research Council’s Dominion Radio Astrophysical Observatory, CMC Microsystems, and TRLabs.

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Correspondence to Leonid Belostotski.

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Belostotski, L., Haslett, J.W. Two-port noise figure optimization of source-degenerated cascode CMOS LNAs. Analog Integr Circ Sig Process 55, 125–137 (2008). https://doi.org/10.1007/s10470-008-9142-4

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