Skip to main content
Log in

Duplicating same argument of function to realize efficient hardware for high-level synthesis

  • Original Article
  • Published:
Artificial Life and Robotics Aims and scope Submit manuscript

Abstract

High-level synthesis (HLS) automatically converting software into hardware is a promising technology to reduce the design burden significantly. However, to use HLS technology efficiently, software program must be described considering the hardware organization that HLS tool will generate. We are developing the HLS image processing library. However, some caution is required when using HLS for programs that read images. When the same image is read through an argument of the function, the input port corresponding to this argument on the hardware generated by HLS tool may cause the port conflict. As a result, the image reading is made serialized and this serialization disturbs the performance of the data path well pipelined by the HLS tool. This paper shows how to write a software program to avoid this problem. In addition, we adapt this method to two image processing and evaluate the effect of our proposal to them.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8

Similar content being viewed by others

References

  1. Nane R, Sima VM, Olivier B, Meeuws R, Yankova Y, Bertels K (2012) DWARV 2.0: a CoSy-based C-to-VHDL hardware compiler. In: Proceedings of 22nd international conference on field programmable logic and applications, Oslo, Norway, 29–31 August 2012, pp 619–622

  2. Pilato C, Ferrandi F (2013) Bambu: a modular framework for the high level synthesis of memory-intensive applications. In: Proceedings of 23rd international conference on field programmable logic and applications, Porto, Portugal, 2–4 September 2013, pp 1–4

  3. Canis A, Choi J, Aldham M, Zhang V, Kammoona A, Anderson JH, Brown S, Czajkowski T (2011) LegUp: high-level synthesis for FPGA-based processor/accelerator systems. In: Proceedings of the 19th ACM/SIGDA international symposium on field programmable gate Arrays, Monterey, CA, USA, 27 February–1 March 2011, pp 33–36

  4. Yamasaki M, Yamawaki A (2019) Describing methods for high-level synthesis of histogram generation and their evaluation. IEIE Trans Smart Proc Comput 8(3):178–185

    Article  Google Scholar 

  5. Yamasaki M, Yonemitsu S, Yamawaki A (2018) Effect of redundant function execution to reduce memory access on high-level synthesis. In: Proceedings of the 6th IIAE international conference on industrial application engineering, Okinawa, Japan, 27–31 March 2018, pp 206–209

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Akira Yamawaki.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

This work was presented in part at the 24th International Symposium on Artificial Life and Robotics, Beppu, Oita, January 23–25, 2019.

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Yamasaki, M., Yamawaki, A. Duplicating same argument of function to realize efficient hardware for high-level synthesis. Artif Life Robotics 25, 248–252 (2020). https://doi.org/10.1007/s10015-019-00576-4

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10015-019-00576-4

Keywords

Navigation