Skip to main content
SpringerLink
Log in

Worst-case execution-time analysis for embedded real-time systems

  • Special section: An experience in the establishment of collaboration between academia and industry
  • Published:
International Journal on Software Tools for Technology Transfer Aims and scope Submit manuscript

Abstract

In this article we give an overview of the worst-case execution time (WCET) analysis research performed by the WCET group of the ASTEC Competence Centre at Uppsala University. Knowing the WCET of a program is necessary when designing and verifying real-time systems. The WCET depends both on the program flow, such as loop iterations and function calls, and on hardware factors, such as caches and pipelines. WCET estimates should be both safe (no underestimation allowed) and tight (as little overestimation as possible). We have defined a modular architecture for a WCET tool, used both to identify the components of the overall WCET analysis problem, and as a starting point for the development of a WCET tool prototype. Within this framework we have proposed solutions to several key problems in WCET analysis, including representation and analysis of the control flow of programs, modeling of the behavior and timing of pipelines and other low-level timing aspects, integration of control flow information and low-level timing to obtain a safe and tight WCET estimate, and validation of our tools and methods. We have focussed on the needs of embedded real-time systems in designing our tools and directing our research. Our long-term goal is to provide WCET analysis as a part of the standard tool chain for embedded development (together with compilers, debuggers, and simulators). This is facilitated by our cooperation with the embedded systems programming-tools vendor IAR Systems.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Audsley, N., Burns, A., Davis, K., Tindell, R., Wellings A.: Fixed priority pre-emptive scheduling: an historical perspective. Real-Time Syst 8(2/3):129–154, 1995

  2. Altenbernd, P.: On the false path problem in hard real-time programs. In: Proc. 8th Euromicro Workshop of Real-Time Systems, pp. 102–107, 1996

  3. ARM (Advanced Risc Machines) WWW Homepage.: URL: http://www.arm.com

  4. Aho, A., Sethi, R., Ullman, J.: Compilers: principles, techniques and tools. Addison-Wesley, Reading, Mass., USA, 1986. Generally known as the “Dragon book”

  5. Bate, I., Bernat, G., Murphy, G., Puschner, P.: Low-level analysis of a portable java byte code WCET analysis framework. In: Proc. 7th International Conference on Real-Time Computing Systems and Applications (RTCSA’00), pp. 39–48, 2000

  6. Bernat, G., Burns, A., Wellings, A.: Portable worst-case execution time analysis using java byte code. In: Proc. 12th Euromicro Conference of Real-Time Systems, (ECRTS’00), pp. 81–88, 2000

  7. Benitez, M.E., Davidson, J.W.: A portable global optimizer and linker. In: Proc. ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI’98), pp. 329–338, June 1988

  8. Bozga, M., Daws, C., Maler, O., Olivero, A., Tripakis, S., Yovine, S.: KRONOS: a model-checking tool for real-time systems. In: Proc. of the 10th International Conference on Computer Aided Verification, Lecture Notes in Computer Science, vol. 1427. Berlin, Heidelberg, New York: Springer, 1998, pp. 546–550

  9. Busquets-Mataix, J.V., Serrano, J.J., Ors, P., Gil, R., Wellings, A.: Adding instruction cache effects to schedulability analysis of preemptive real-time systems. In: Proc. 2nd IEEE Real-Time Technology and Applications Symposium (RTAS’96), June, pp. 204–212. IEEE Computer Society, New York, 1996

  10. Börjesson, H.: Incorporating worst-case execution time in a commercial c-compiler. Master’s thesis, Department of Computer Systems, Uppsala University, December 1995. DoCS MSc Thesis 95/69

  11. Bermudo, N., Vera, X., González, A., Llosa, J.: An efficient solver for cache miss equations. In: IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS’00), 2000

  12. Chapman, R., Burns, A., Wellings, A.: Integrated program proof and worst-case timing analysis of SPARK Ada. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems (LCT-RTS’94), 1994

  13. Cousot, P.: Abstract interpretation. ACM Comput Surv 28(2):324–328, 1996

  14. Colin, A., Puaut, I.: Worst case execution time analysis for a processor with branch prediction. J Real-Time Syst May 2000

  15. Colin, A., Puaut, I.: A modular and retargetable framework for tree-based WCET analysis. In: Proc. 13th Euromicro Conference of Real-Time Systems, (ECRTS’01), June 2001

  16. Colin, A., Puaut, I.: Worst-case execution time analysis for the RTEMS real-time operating system. In: Proc. 13th Euromicro Conference of Real-Time Systems, (ECRTS’01), June 2001

  17. Casparsson, L., Rajnak, A., Tindell, K., Malmberg, P.: Volcano – a revolution in on-board communications. Volvo Technology Report, 1:9–19, 1998

  18. Dean, A., Shen, J.P.: System-level issues for software thread integration: guest triggering and host selection. In: Proc. 20th IEEE Real-Time Systems Symposium (RTSS’99), 1999

  19. Engblom, J., Altenbernd, P., Ermedahl, A.: Facilitating worst-case execution times analysis for optimized code. In: Proc. 10th Euromicro Workshop of Real-Time Systems, pp. 146–153, June 1998

  20. Engblom, J., Ermedahl, A.: Pipeline timing analysis using a trace-driven simulator. In: Proc. 6th International Conference on Real-Time Computing Systems and Applications (RTCSA’99). IEEE Computer Society Press, December 1999

  21. Engblom, J., Ermedahl, A.: Modeling complex flows for worst-case execution time analysis. In: Proc. 21st IEEE Real-Time Systems Symposium (RTSS’00), November 2000

  22. Engblom, J., Ermedahl, A.: Validating a worst-case execution time analysis method for an embedded processor. In: Work-in-Progress Session, 21st IEEE Real-Time Systems Symposium (RTSS’00), November 2000

  23. Ermedahl, A., Gustafsson, J.: Deriving annotations for tight calculation of execution time. In: Proc. 3rd International European Conference on Parallel Processing, (Euro-Par’97), Lecture Notes in Computer Science, vol. 1300. Berlin, Heidelberg, New York: Springer, 1998, pp. 1298–1307

  24. Engblom, J.: Worst-case execution time analysis for optimized code. Master’s thesis, Department of Computer Systems, Uppsala University, September 1997. DoCS MSc Thesis 97/94

  25. Engblom, J.: Static properties of embedded real-time programs, and their implications for worst-case execution time analysis. In: Proc. 5th IEEE Real-Time Technology and Applications Symposium (RTAS’99). IEEE Computer Society, New York, 1999

  26. Erpenbach, E., Stappert, F., Stroop, J.: Compilation and timing analysis of statecharts models for embedded systems. In: Proc. 2nd International Workshop on Compiler and Architecture Support for Embedded Systems, (CASES’99), October 1999

  27. Ernst, R., Ye, W.: Embedded program timing analysis based on path clustering and architecture classification. In: International Conference on Computer-Aided Design (ICCAD ’97), 1997

  28. Ferdinand, C., Martin, F., Wilhelm, R.: Applying compiler techniques to cache behavior prediction. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems (LCT-RTS’97), 1997

  29. Gustafsson, J., Ermedahl, A.: Automatic derivation of path and loop annotations in object-oriented real-time programs. J Parallel Distrib Comput Pract 1998

  30. Ghosh, S., Martonosi, M., Malik, S.: Cache miss equations: a compiler framework for analyzing and tuning memory behavior. In: ACM Transactions on Programming Languages and Systems, 1998

  31. Gustafsson, J.: Analyzing execution-time of object-oriented programs using abstract interpretation. PhD thesis, Department of Computer Systems, Information Technology, Uppsala University, May 2000

  32. Halfhill, T.R.: Embedded market breaks new ground. Microprocessor Report, January 17, 2000

  33. Healy, C., Arnold, R., Müller, F., Whalley, D., Harmon, M.: Bounding pipeline and instruction cache performance. IEEE Trans Comput 48(1), 1999

  34. Henzinger, T.A., Ho, P-H., Wong-Toi, H.: HYTECH: a model checker for hybrid systems. In: Proc. of the 9th International Conference on Computer Aided Verification, Lecture Notes in Computer Science, vol. 1254. Berlin, Heidelberg, New York: Springer, 1997, pp. 460–463

  35. Holzmann, G.J.: The model checker spin. IEEE Trans Software Eng 23(5):279–295, 1997

  36. Healy, C., Sjödin, M., Rustagi, V., Whalley, D., van Engelen, R.: Supporting timing analysis by automatic bounding of loop iterations. J Real-Time Syst May 2000

  37. Healy, C., Sjödin, M., Rustagi, V., Whalley, D.: Bounding loop iterations for timing analysis. In: Proc. 4th IEEE Real-Time Technology and Applications Symposium (RTAS’98), June 1998

  38. I-Logix WWW Homepage.: URL: http://www.ilogix.com/smover_c.htm

  39. IAR Systems WWW Homepage.: URL: http://www.iar.com

  40. IAR Systems.: Reference Applications of VisualSTATE. http://www.iar.dk/products/references.htm

  41. IAR Systems.: V850 C/EC++ Compiler Programming Guide, 1st edn. January 1999

  42. ISL (Intelligent Systems Laboratory).: SICStus Prolog user’s manual. ISBN 91-630-3648-7, Swedish Institute of Computer Science, 1995

  43. Kim, S.-K., Min, S.L., Ha, R.: Efficient worst case timing analysis of data caching. In: Proc. 2nd IEEE Real-Time Technology and Applications Symposium (RTAS’96), pp. 230–240, 1996

  44. Lim, S.-S., Bae, Y.H., Jang, C.T., Rhee, B.-D., Min, S.L., Park, C.Y., Shin, H., Park, K., Ki, C.S.: An accurate worst-case timing analysis for RISC processors. IEEE Trans Software Eng 21(7):593–604, 1995

  45. Liu, Y.A., Gomez, G.: Automatic accurate time-bound analysis for high-level languages. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES’98), 1998

  46. Lim, S.-S., Han, J.H., Kim, J., Min, S.L.: A worst case timing analysis technique for multiple-issue machines. In: Proc. 19th IEEE Real-Time Systems Symposium (RTSS’98), December 1998

  47. Lee, C., Han, J., Seo, Y., Min, S., Ha, R., Hong, S., Park, C., Lee, M., Kim, C.: Analysis of cache-related preemption delay in fixed-priority preemptive scheduling. In: Proc. 17th IEEE Real-Time Systems Symposium (RTSS’96), December 1996

  48. Lindgren, M.: Measurements and simulation based techniques for real-time systems analysis. Licentiate Thesis, Uppsala University of Technology, Uppsala, Sweden, 2000

  49. Lim, S-S., Kim, J., Min, S.L.: A worst case timing analysis technique for optimized programs. In: Proc. 5th International Conference on Real-Time Computing Systems and Applications (RTCSA’98), pp. 151–157, Oct 1998

  50. Liu, C., Layland, J.: Scheduling algorithms for multiprogramming in a hard-real-time environment. J ACM, 20(1):46–61, 1973

  51. Li, Y-T.S., Malik, S.: Performance analysis of embedded software using implicit path enumeration. In: Proc. of the 32nd Design Automation Conference, pp. 456–461, 1995

  52. Li, Y-T.S., Malik, S., Wolfe, A.: Cache modelling for real-time software: beyond direct mapped instruction caches. In: Proc. 17th IEEE Real-Time Systems Symposium (RTSS’96), pp. 254–263. IEEE Computer Society, December 1996

  53. Larsen, K.G., Pettersson, P., Yi, W.: Uppaal in a nutshell,. Int J Software Tools Technol Transfer 1(1–2):134–152, 1997

  54. Lundqvist, T., Stenström, P.: Integrating path and timing analysis using instruction-level simulation techniques. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES’98), June 1998

  55. Microprocessor Report.: Tera-Gen Reveals 8-bit Threaded Processor. Microprocessor Report, January 25, 1999

  56. Muchnick, S.S.: Advanced compiler design. San Francisco: Morgan Kaufmann, 1997

  57. Müller, F.: Timing predictions for multi-level caches. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems (LCT-RTS’97), pp. 29–36, Jun 1997

  58. NEC Corporation.: V850E/MS1 32/16-bit Single Chip Microcontroller: Architecture, 3rd edn. January 1999. Document no. U12197EJ3V0UM00

  59. Ottosson, G., Sjödin, M.: Worst-case execution time analysis for modern hardware architectures. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems (LCT-RTS’97), June 1997

  60. Park, C.Y.: Predicting program execution times by analyzing static and dynamic program paths. Real-Time Syst 5(1):31–62, 1993

  61. Petters, S., Färber, G.: Making worst-case execution time analysis for hard real-time tasks on state of the art processors feasible. In: Proc. 6th International Conference on Real-Time Computing Systems and Applications (RTCSA’99), December 1999

  62. Persson, P., Hedin, G.: Interactive execution time predictions using reference attributed grammars. In: Proc. of the 2nd Workshop on Attribute Grammars and their Applications (WAGA’99), Amsterdam, Netherlands, pp. 173–184, August 1998

  63. Puschner, P., Koza, C.: Calculating the maximum execution time of real-time programs. J Real-Time Syst, 1(1):159–176, 1989

  64. Park, C.Y., Shaw, A.C.: Experiments with a program timing tool based on a source-level timing schema. In: Proc. 11th IEEE Real-Time Systems Symposium (RTSS’90), pp. 72–81, December 1990

  65. Puschner, P., Schedl, A.: Computing maximum task execution times with linear programming techniques. Technical report, Technische Universität, Institut für Technische Informatik, Wien, April 1995

  66. Raymond, E.: The Jargon File, version 4.2.0. URL: http://www.tuxedo.org/~esr/jargon/html/index.html, February 2000

  67. Runeson, J.: Code compression through procedural abstraction before register allocation. Master’s thesis, Department of Information Technology, Uppsala University, March 2000

  68. Stappert, F., Altenbernd, P.: Complete worst-case execution time analysis of straight-line hard real-time programs. J Syst Archit 46(4):339–355, 2000

  69. Scenix Semiconductor Inc.: Scenix SX Family User’s Manual, 3rd edn. 2000

  70. Schneider, J.: Cache and pipeline sensitive fixed priority scheduling for preemptive real-time systems. In: Proc. 21st IEEE Real-Time Systems Symposium (RTSS’00), pp. 195–204, Nov 2000

  71. Schneider, J., Ferdinand C.: Pipeline behaviour prediction for superscalar processors by abstract interpretation. In: Proc. ACM SIGPLAN Workshop on Languages, Compilers and Tools for Embedded Systems (LCTES’99), May 1999

  72. Seppänen, V., Kähkönen, A-M., Oivo, M., Perunka, H., Isomursu, P., Pulli, P.: Strategic needs and future trends of embedded software. Technical Report Technology Review 48/96, TEKES Technology Development Center, Oulu, Finland, October 1996

  73. Telelogic WWW Homepage.: URL: http://www.telelogic.com/tau4

  74. David Tennenhouse (Intel Director of Research).: Keynote Speech at the 20th IEEE Real-Time Systems Symposium (RTSS’99), Phoenix, Ariz., December 1999

  75. White, R., Müller, F., Healy, C., Whalley, D., Harmon, M.: Timing Analysis for Data Caches and Set-Associative Caches. In: Proc. 3rd IEEE Real-Time Technology and Applications Symposium (RTAS’97), pp. 192–202, June 1997

Download references

Author information

Authors and Affiliations

  1. Department of Information Technology, Uppsala University, Uppsala, Sweden

    Jakob Engblom , Andreas Ermedahl  & Hans Hansson

  2. IAR Systems, Uppsala, Sweden

    Jakob Engblom

  3. Melody Interactive Solutions, Uppsala, Sweden

    Mikael Sjödin

  4. Mälardalen Real-Time Research Centre, Mälardalen University, Västerås, Sweden

    Jan Gustafsson  & Hans Hansson

Authors
  1. Jakob Engblom
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Andreas Ermedahl
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Mikael Sjödin
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Jan Gustafsson
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. Hans Hansson
    View author publications

    You can also search for this author in PubMed Google Scholar

Rights and permissions

Reprints and permissions

About this article

Cite this article

Engblom , J., Ermedahl , A., Sjödin , M. et al. Worst-case execution-time analysis for embedded real-time systems. STTT 4, 437–455 (2003). https://doi.org/10.1007/s100090100054

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s100090100054

Keywords

Search

Navigation