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System architecture evaluation using modular performance analysis: a case study

  • Special Section on Quantitative Analysis of Real-time Embedded Systems
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Abstract

Performance analysis plays an increasingly important role in the design of embedded real-time systems. Time-to-market pressure in this domain is high while the available implementation technology is often pushed to its limit to minimize cost. This requires analysis of performance as early as possible in the life cycle. Simulation-based techniques are often not sufficiently productive. We present an alternative, analytical, approach based on Real-Time Calculus. Modular performance analysis is presented through a case study in which several candidate architectures are evaluated for a distributed in-car radio navigation system. The analysis is efficient due to the high abstraction level of the model, which makes the technique suitable for early design exploration.

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References

  1. Bacelli F., Cohen G., Olsder G.J., Quadrat J.P.(1992): Synchronization and Linearity: An Algebra for Discrete Event Systems.Wiley Series in Probability and Mathematical Statistics. John Wiley & Sons Ltd, New York

    Google Scholar 

  2. Balsamo S., Di Marco A., Inverardi P.(2004): Model-based performance prediction in software development: A survey. IEEE Trans Softw Eng 30(5): 295–310

    Article  Google Scholar 

  3. Chakraborty, S., Künzli, S., Thiele, L.: A general framework for analysing system properties in platform-based embedded system designs. In: Proceedings of 6th Design, Automation and Test in Europe (DATE), Munich, Germany, pp. 190–195 (2003)

  4. Cortellessa, V., Mirandola, R.: Deriving a queueing network based performance model from UML diagrams. In: Proceedings of 2nd International Workshop on Software and Performance (WOSP), Ottawa, Ontario, Canada, pp. 58–70 (2000)

  5. Cruz R.L.(1991): A calculus for network delay. IEEE Trans Information Theory 37(1): 114–141

    Article  MathSciNet  Google Scholar 

  6. Gries, M.: Methods for evaluating and covering the design space during early design development. Tech. Rep. UCB/ERL M03/32, Electronics Research Lab, University of California at Berkeley (2003)

  7. Grotker T., Liao S., Martin G., Swan S.(2002): System Design with SystemC. Kluwer, Dordrecht

    Google Scholar 

  8. IEEE/EIA: ISO/IEC 12207:1995 Standard for Information Technology – Software life cycle processes. The Institute of Electrical and Electronics Engineers, Inc. (1998)

  9. Kienhuis, B., Deprettere, E., Vissers, K., van der Wolf, P.: An approach for quantitative analysis of dataflow architectures. In: ASAP ’97: Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, IEEE Computer Society, Washington, DC, USA, p. 338 (1997)

  10. Le Boudec J.Y., Thiran P.(2001): Network Calculus - A Theory of Deterministic Queuing Systems for the Internet No. 2050 in Lecture Notes in Computer Science (LNCS). Springer, Berlin Heidelberg New York

    Google Scholar 

  11. Maxiaguine A., Chakraborty S., Künzli S., Thiele L.(2004): Evaluating schedulers for multimedia processing on buffer-constrained soc platforms. IEEE Design Test 21(5): 368–377

    Article  Google Scholar 

  12. Maxiaguine, A., Künzli, S., Thiele, L.: Workload characterization model for tasks with variable execution demand. In: Proceedings of 7th Design, Automation and Test in Europe (DATE) (2004)

  13. Object Management Group: UML Profile for Schedulability, Performance and Time Specification (2004). URL http://www.uml.org/. Version 1.1, ptc/04-02-01

  14. Schioler, H., Larsen, K.G., Jessen, J., Dalsgaard, J.: Cync - a method for real time analysis of systems with cyclic data flows. In: Proceedings of the 13th International Conference on Real-Time Systems, Automation and Test in Europe (RTS). Paris, France (2005)

  15. Shin, I., Lee, I.: Periodic resource model for compositional real-time guarantees. In: Proceedings of the Real-Time Systems Symposium (RTSS), IEEE Press, pp. 2–13 (2003)

  16. Smith, C.U., Williams, L.G.: Computer Performance Evaluation: Modeling Techniques and Tools, chap. Performance Engineering Evaluation of Object-Oriented Systems with SPE*ED. No. 1245 in Lecture Notes in Computer Science (LNCS). Springer, Berlin Heidelberg New York (1997)

  17. Thiele, L., Chakraborty, S., Naedele, M.: Real-Time Calculus for scheduling hard real-time systems. In: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS), vol. 4, pp. 101–104 (2000)

  18. Wandeler, E., Maxiaguine, A., Thiele, L.: Quantitative characterization of event streams in analysis of hard real-time applications. In: 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) (2004)

  19. Wandeler, E., Thiele, L.: Abstracting functionality for modular performance analysis of hard real-time systems. In: Asia South Pacific Design Automation Conference (ASP-DAC) (2005)

  20. Wandeler, E., Thiele, L.: Characterizing workload correlations in multi processor hard real-time systems. In: 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), IEEE, San Francisco, USA, pp. 46–55 (2005)

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Authors and Affiliations

  1. ETH Zürich, Information Technology and Electrical Engineering Department, Computer Engineering and Networks Laboratory (TIK), Gloriastrasse 35, 8092, Zürich, Switzerland

    Ernesto Wandeler & Lothar Thiele

  2. Chess Information Technology, B.V., Nieuwe Gracht 13, 2011, NB, Haarlem, The Netherlands

    Marcel Verhoef

  3. Institute for Computing and Information Sciences, Radboud University Nijmegen, Nijmegen, The Netherlands

    Marcel Verhoef

  4. Siemens VDO Trading B.V., Luchthavenweg 48, 5657, EB, Eindhoven, The Netherlands

    Paul Lieverse

Authors
  1. Ernesto Wandeler
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  2. Lothar Thiele
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  3. Marcel Verhoef
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  4. Paul Lieverse
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Corresponding author

Correspondence to Ernesto Wandeler.

Additional information

This work has been carried out as part of the boderc project under the responsibility of the Embedded Systems Institute

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Wandeler, E., Thiele, L., Verhoef, M. et al. System architecture evaluation using modular performance analysis: a case study. Int J Softw Tools Technol Transfer 8, 649–667 (2006). https://doi.org/10.1007/s10009-006-0019-5

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  • DOI: https://doi.org/10.1007/s10009-006-0019-5

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