Abstract
Digital down converter (DDC) is one of the crucial components in digital radio receiver. The working function of DDC is to convert the frequency translation from Intermediate Frequency (IF) band to baseband signal. This paper briefs a hardware efficient DDC architecture which is made of COordinate Rotation Digital Computer (CORDIC) processor act as a digital oscillator followed by multi-stage Cascaded Integrator Comb (CIC) performs as a high rate decimation filter and then Multi-channel Systolic Finite Impulse Response (MSFIR) decimation filter allows perfect output. All of these components of the proposed DDC architecture have been designed in Xilinx ISE 14.7 simulator using optimization techniques and targeted to the Xilinx Kintex-7 Field Programmable Gate Array (FPGA) device. Implementation of DDC on FPGA provides high flexibility, moderate cost and customizability. The result analysis of the proposed DDC model is superior to the similar design with regard to area, operating speed and power consumption. The implemented DDC design is used to transform input bandwidth from about 70 MHz to 137 kHz, matching in Software Defined Radio (SDR) system requirements.
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The authors would like to thank Brainware Group of Institutions and Kalyani Government Engineering College for providing the ISE design suite 14.7 and Xilinx FPGA device.
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Datta, D., Mitra, P. & Dutta, H.S. FPGA implementation of high performance digital down converter for software defined radio. Microsyst Technol 28, 533–542 (2022). https://doi.org/10.1007/s00542-019-04579-w
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DOI: https://doi.org/10.1007/s00542-019-04579-w