Advances in active down-conversion mixer linearity techniques: a comprehensive review

Abstract

In the modern era, the demand for high-speed communication has led to a growing preference for higher bandwidth. However, in wideband scenarios, the presence of neighboring bands can introduce nonlinearity issues in mixers. The RF stage and Switching stage are identified as the primary contributors to nonlinearity in down-conversion mixers. This article presents a basic principle as well as circuit architectures of the mixer, including a performance parameters comprehensive review of linearity improvement techniques employed in down-conversion mixers. The paper categorizes various previously reported methods to enhance the linearity of the RF stage into five approaches: (1) MGTR/Derivative superposition (DS), (2) Complementary DS (CDS), (3) noise cancellation (NC), (4) post distortion (PD), and (5) feedforward or feedback approach. These techniques aim to enhance the Second-order nonlinearity ($g_{m}^{\prime }$) or third-order nonlinearity ($g_{m}^{\prime \prime }$) of the RF stage. Among these approaches, Noise Cancellation (NC) methods demonstrate superior optimization in terms of Conversion Gain, Linearity, and Noise Figure. Furthermore, to improve the linearity of the switching stage in mixers, the static and dynamic current injection methods can be employed. The objective of this review is to contribute to the advancement of linearity improvement techniques for wideband active down-conversion mixers, while also facilitating future research and development in this field.

1 Introduction

The demand for fast data-rate wireless communication is experiencing rapid growth in today’s world, especially in urban areas, placing significant emphasis on the RF Front end (RFFE), which must operate across a wide range of frequencies [1]. Several receiver architectures are available for implementing wireless systems, including super-heterodyne, low IF, direct conversion, image rejection, and digital IF receivers [2]. Among these, the low IF architecture shown in Fig. 1 is a preferred solution for wideband applications due to its ability to eliminate DC offsets and the tendency to reduce the flicker (1/f) noise [3, 4].

Fig. 1

Direct-conversion Receiver architectures for Ultra-Wideband (UWB) [2]

The RF Front End (RFFE) comprises several crucial elements, such as low noise amplifiers (LNA),down-conversion mixers, and oscillators (VCO). Among these components, the performance of the LNA - MIXER pair plays a pivotal role in the overall performance of the RFFE, including aspects like linearity, Noise Figure (NF), and Conversion gain. Therefore, it is essential to enhance the performance of the LNA–MIXER pair simultaneously to achieve significant improvements in the overall RFFE performance [5].

The upper limit of the dynamic range in the Radio Frequency Front-End (RFFE) system is determined by linearity [6], with the lower limit influenced by system noise. The Noise Figure (NF) of the mixer significantly impacts RF system performance, affecting both received and processed signals. Implementing mixers with CMOS technology ensures optimal performance, characterized by low power consumption and high integration density [7, 8].

The CMOS mixer can be divided into two types: active and passive. The active mixer utilizes a current signal for frequency conversion, while the passive mixer employs a voltage signal for the conversion. Passive mixers showcase advantages such as less flicker noise (1/f), superior linearity, and wideband properties compared to their active counterparts [5]. However, passive mixers require higher LO signal power for driving, leading to inherent conversion losses, poor reverse isolation, and potential issues with larger noise coefficients and troublesome IQ crosstalk. As a remedy, compensatory peripheral circuits become necessary for passive mixers.

On the flip side, active mixers demand less LO signal power, offer higher conversion gain ($G_{c}$) performance, and provide better isolation between RF, LO, and IF ports than passive mixers, enhancing noise rejection for subsequent circuit modules [9]. Nevertheless, they tend to exhibit lower linearity compared to passive mixers [2]. The choice between active and passive mixers in the design process must be made based on the expected performance index (Table 1). With the continuous improvement in mixer performance, most mixers now include modules based on the Gilbert double-balanced mixer [10].

Table 1 Comparison table of active mixers and passive mixers

The active mixer consists of two types [11]:

• Switched Transconductance (Sw+Gm) Mixer: The mixers depicted in Fig. 2 utilize Switched Transconductance (Sw+Gm) technology, employing four CS MOSFETs ($M_{3}$–$M_{6}$) within their RF input stage to create RF transconductance pairs. These mixers also feature an LO switching stage ($M_{1}$–$M_{2}$) that operates differentially, modulating the bias current ($I_{B}$+$i_{RF}$) that passes through the RF transconductance pairs. Furthermore, they incorporate a load stage ($R_{L}$) where periodically commutated RF signal current is transformed into an IF signal voltage. The Sw+Gm Mixer demonstrates superior thermal noise performance due to minimal noise from switching devices, making it advantageous for applications with low-voltage requirements. This aspect is emphasized in an analysis detailed in [12], focusing on a mixer tailored for low-voltage operation challenges. It achieves competitive performance at reduced supply voltages by employing switches tied exclusively to supply voltages. This design choice addresses gate-oxide reliability issues and minimizes voltage headroom requirements by employing two transconductors with cross-coupled outputs activated by switches, effectively competing with traditional mixers. Moreover, the integration of low-ohmic switches minimizes voltage drop, maximizing supply voltage headroom and enhancing conversion gain. Furthermore, [11] presents a mathematical model addressing flicker noise mechanisms in Switching Transconductance (Sw+Gm) mixers, along with challenges posed by parasitic capacitance at high frequencies (HF). Additionally, in [13], the Sw+Gm mixer is evaluated for its high mixer common-mode rejection ratio (MCMRR). Recommendations from this analysis include utilizing sinusoidal LO driving for noise advantages and integrating an inductor resonating structure to tackle operation frequency limitations due to tail parasitic capacitances. The paper also discusses strategies for reducing flicker noise in mixers designed for direct-conversion receivers, such as incorporating a PMOS transconductance structure.

  Fig. 2

  

  Double balanced mixer (Sw+Gm) configuration

• Gilbert (Gm+Sw) Mixers: These mixers utilize LO switch pairs ($M_{3}$–$M_{6}$) to modulate the RF current ($I_{B}$+$i_{RF}$) from an RF transconductance stage($M_{1}$–$M_{2}$), controlled by a large LO signal. This process completes the frequency conversion from RF to IF. The configuration of this Gilbert cell mixer is illustrated in Figs. 3 and 4. The operational aspects of this mixer type are extensively discussed in [14].

  Fig. 3

  

  Double balanced mixer (Gm+Sw) configuration [19]

  Fig. 4

  

  Single balanced mixer configuration [19]

Table 2 presents a discussion comparing Gilbert (Gm+Sw) Mixers with Switched Transconductance (Sw+Gm) Mixers. Moreover, as the number of cascaded stages increases, there is a corresponding increase in nonlinearity and noise, leading to various effects such as harmonic distortion, intermodulation, cross-modulation, gain compression, and desensitization [4]. Therefore, the role of the mixer is crucial as it directly influences the linearity (IIP2, IIP3), noise figure (NF), and conversion gain ($G_{c}$).

Table 2 Comparison table of Gilbert (Gm+Sw) mixers and switched-gm (Sw+Gm) mixers [12]

Designing down-conversion active mixers for wideband applications requires special attention to linearity due to 2nd order intermodulation (IM2) and 3rd order intermodulation (IM3) occurring within the frequency bands [2]. Therefore, ensuring high linearity is vital to mitigate the impact of these intermodulation distortions in wideband scenarios.

The Active double-balanced mixer consists of 3 stages [10]:

• (i) RF transconductance stage ($M_{1}$–$M_{2}$): This stage converts the RF voltage signal into current, utilizing a biased differential pair that functions as the RF transconductance amplifier.

• (ii) Switching Stage ($M_{3}$–$M_{6}$): Driven by a local oscillator signal (LO), the switching stage ($M_{3}$–$M_{6}$) is tasked with performing the mixing operation.

• (iii) Load/IF Stage ($R_{L}$): This stage plays a dual role by converting current to IF voltage and serving as the load for the mixer. Additionally, it functions as the intermediate frequency (IF) amplifier.

The operation of the active mixer is extensively discussed in [14]. The double-balanced structure provides advantages such as LO rejection, rejection of even-order distortion products, higher conversion gain ($G_{c}$), and improved noise performance. However, it exhibits considerably worse linearity [5, 15] and flicker noise performance [12].

Flicker noise (1/f noise), becomes a significant consideration especially when mixers are used in Direct Conversion Receivers (DCR) applications. This type of noise manifests in all three stages of the mixer: the RF stage, the load stage, and particularly in the switching MOS devices.

RF Stage Flicker noise is up-converted into LO frequency and that does not appear at the baseband [14]. Properly sizing active load devices or using poly resistors in the mixer can minimize flicker noise in the load stage. major concern about the Switching noise: Mismatches in the switching pair contribute to flicker noise which is extensively discussed in [16]. Various techniques have been reported to reduce flicker noise in CMOS active mixers, such as negative Impedance [16], dynamic current injection [17] and RF leakageless static current bleeding with resonating inductors [18]. These methods aim to enhance mixer performance, particularly in applications demanding low noise and high linearity for the Direct Conversion Receivers (DCR) applications.

2 Sources of non-linearity in mixer

The active mixer consists of 3 stages: RF transconductance, switching, and load/IF. Non-linearity in mixers can be traced back to two main stages:

• 1. RF transconductance stage: The primary source of non-linearity in this stage is attributed to the MOSFET ($M_{1}$–$M_{2}$), as discussed in Sect. 2.1.

• 2. Switching stage: The non-linearity of the mixer is influenced by the non-ideal switching behavior exhibited by MOSFETs ($M_{3}$–$M_{6}$), as discussed in Sect. 2.2.

These two stages, RF transconductance and switching play significant roles in the occurrence of non-linearity in the active mixer, and their effects are thoroughly explored in the respective sections of the paper.

2.1 Transconductance stage non-linearity (RF stage $M_{1}$–$M_{2}$)

Active mixer gets an amplified version of the input from LNA ($v_{RF}$) and converts it into current ($i_{RF}$) through the of RF MOSFET ($M_{1}$–$M_{2}$) as shown in Fig. 3.

The non-linearity introduced by the RF stage originates from two sources [20, 21]:

• 1. Transconductance ($g_{m}$): Converts the linear input ($v_{RF}$) into non-linear output current ($i_{RF}$).

• 2. Non-linear output conductance ($g_{ds}$): The effect of this component becomes noticeable when there is a high output voltage swing at the drain node of ($M_{1}$–$M_{2}$).

The non-linear behavior exhibited by the RF stage ($M_{1}$), as illustrated in Fig. 4, can be modeled using a power series, with the higher-order coefficients being omitted.

$$i_{{RF}} = g_{{m1}} v_{{RF}} + \frac{{g_{{m1}}^{\prime } }}{{2!}}v_{{RF}}^{2} + \frac{{g_{{m1}}^{{\prime \prime }} }}{{3!}}v_{{RF}}^{3} +$$

(1)

where

$$\begin{aligned} \begin{aligned} g_{m1}=\frac{\partial \ I_{DS}}{\partial \ V_{GS}},{\ g}_{m1}^\prime =\frac{\partial ^2I_{DS}}{\partial \ V_{GS}^2},\ g_{m1}^{\prime \prime }=\frac{\partial ^3I_{DS}}{\partial \ V_{GS}^3} \end{aligned} \end{aligned}$$

(2)

$$\begin{aligned} \begin{aligned} IIP3=\sqrt{\frac{4}{3}\left| \frac{g_{m1}}{g_{m1}^{''}}\right| } \end{aligned} \end{aligned}$$

(3)

where $g_{m1}$ = Transconductance of MOSFET $M_{1}$ and $i_{RF}$ = Output current of MOSFET $M_{1}$.

Figure 5 illustrates the simulated profile of 2nd order non-linearity ($g_{m1}^{\prime }$) and 3rd order non-linearity ($g_{m1}^{\prime \prime }$) for the RF stage ($M_{1}$). The presence of non-zero $g_{m}^{\prime }$ and $g_{m}^{\prime \prime }$ of the RF stage degrades the IIP3 (third-order intercept point) performance of the mixer according to Eq. 3. Consequently, different techniques have been reported in the literature [20, 21] to mitigate or nullify the effects of $g_{m}^{\prime }$ and $g_{m}^{\prime \prime }$ of the RF stage ($M_{1}$). These techniques include (1) Multiple Gated Transistor (MGTR)/Derivative Superposition (DS) [15, 22,23,24], (2) Complementary Derivative Superposition (CDS) [25,26,27], (3) Noise/Distortion cancellation (NC) [24, 28,29,30,31,32], (4) Post Distortion (PD) [33, 34], and (5) Feedback Approach [35].

Fig. 5

RF stage MOS ($M_{1}$) transconductance profile (gpdk 90nm CMOS process, W/L = 120/100, Vds = 1 Volt) [19]

2.2 Switching stage non-linearity ($M_{3}$–$M_{4}$)

The mixing process takes place in the switching stage ($M_{3}$–$M_{4}$), where the current ($i_{RF}$) is combined with the LO signals, as depicted in Fig. 4. The desired condition for an ideal mixing operation is to have one MOSFET in the switching stage in the ON state while the other MOSFET is in the OFF state. However, in practical scenarios, achieving this ideal condition is not possible due to the sinusoidal nature of the Local Oscillator (LO) signal. The sinusoidal LO signal causes both the switching stage MOSFETs to be turned ON simultaneously for a certain period [19]. To ensure that both the RF stage ($M_{1}$) and the switching MOSFETs ($M_{3}$–$M_{4}$) remain in the saturation regime, the voltage at the drain node of the switching MOSFETs must be sufficiently high. If the voltage at the drain node of the switching MOSFETs is not adequately high, the switching MOSFETs ($M_{3}$–$M_{4}$) will operate in the triode region, introducing non-linearity into the switching stage [36].

The small signal current ($i_{01}$) of an $M_{3}$ is a function of the instantaneous values of the transconductance stage’s output current ($i_{RF}$) and Local oscillator voltage $V_{LO}(t)$ shown in Fig. 6. This relationship can be represented by the equation:

$$\begin{aligned} \begin{aligned} I_{01}+i_{01}=Function\ \left( V_{LO}\left( t\right) ,i_{RF}+I_B\right) . \end{aligned} \end{aligned}$$

(4)

In the equation above, $I_{B}$ and $i_{01}$ represent the DC currents resulting from the biasing conditions Comparison table of Gilbert (Gmat the RF stage and the output of the LO stage, respectively. The third-order Taylor expression of Eq. 5

$$\begin{aligned} \begin{aligned} i_{01}= q_{1}(t)i_{RF} + \frac{1}{2}q_{2}(t)i_{RF}^{2} + \frac{1}{6}q_{3}(t)i_{RF}^{3} \end{aligned} \end{aligned}$$

(5)

where

$$\begin{aligned} \begin{aligned} q_{1}(t)=\frac{\partial \ F}{\partial \ I_{B}}, q_{2}(t)=\frac{\partial \ ^2F}{\partial \ I_{B}^2} q_{3}(t)=\frac{\partial \ ^3F}{\partial \ I_{B}^3} \end{aligned} \end{aligned}$$

(6)

Periodic waveforms of non-linearity coefficients are shown in Fig. 6. For sinusoidal LO, will be non-zero for the time interval $\left( \Delta \right)$ in which either $M_{2}$ or $M_{3}$ enters in triode regime before the other MOSFET turns OFF. This deteriorates the linearity of mixer [19].

Fig. 6

Typical waveforms of $(q_1\left( t\right) {,\ q}_2\left( t\right) \,and \ q_3\left( t\right) )$ [19]

3 Linearization methods

In an active CMOS mixer, the non-linearity of the RF transconductor stage MOSFETs ($M_{1}$–$M_{2}$) can be mitigated by canceling out the effects of $g_{m}^{\prime }$ and $g_{m}^{\prime \prime }$. Similarly, to enhance the linearity of the switching stage, it is important to maintain a sufficient voltage at the drain node of ($M_{3}$–$M_{4}$) to prevent these MOSFETs from entering the triode region [17], as well as to keep $M_{1}$ and $M_{2}$ in the saturation regime.

Sections 3.1 to 3.4 discuss various methods for boosting the linearity of the RF transconductor stage. On the other hand, Sect. 3.5 specifically focuses on techniques to enhance the non-linearity of the switching stage.

3.1 Multiple gated transistor (MGTR)/derivative superposition (DS)

The simulations of $g_{m1}^{\prime }$ and $g_{m1}^{\prime \prime }$ for the RF stage MOSFET ($M_{1}$) are depicted in Fig. 5. The profile of $g_{m1}^{\prime \prime }$ exhibits both a positive peak and a negative peak. In order to mitigate the impact of $g_{m1}^{\prime \prime }$, an auxiliary MOSFET ($M_{1A}$) is introduced and connected in parallel with $M_{1}$, as depicted in Fig. 7. The Simulation results presented in Figs. 8 and 9. By precisely adjusting the biasing voltage for the weak inversion region and sizing of the auxiliary MOSFET ($M_{1A}$), it is possible to achieve cancellation by overlapping the negative peak of $g_{m1}^{\prime \prime }$ for $M_{1}$ and the positive peak of $g_{m1A}^{\prime \prime }$ for $M_{1A}$. Consequently, the overall value of $g_{m1}^{\prime \prime }+g_{m1A}^{\prime \prime }$ becomes zero as shown in Fig. 9, effectively eliminating the undesired non-linearity caused by $g_{m1}^{\prime \prime }$. This cancellation technique helps in enhancing the linearity of the RF stage by minimizing the distortions introduced by $g_{m1}^{\prime \prime }$.

Fig. 7

Derivative superposition technique

However, utilizing a single auxiliary MOSFET ($M_{1A}$) has limitations in terms of achieving a corrected flat zone due to the asymmetrical positive and negative properties. To extend the flat zone and improve linearity, multiple auxiliary MOSFETs can be connected in parallel with $M_{1}$. However, this approach leads to gain degradation due to increased parasitic capacitance [20]. The $g_{m1}^{\prime }$ and $g_{m1A}^{\prime }$ profiles for transistors $M_{1}$ and $M_{1A}$ exhibit only a positive peak as depicted in Fig. 8. Biasing $M_{1}$ and $M_{1A}$ to mitigate 3rd order non-linearity reduces $g_{m}^{\prime \prime }$ but introduces 2nd order non-linearity in the form of increased total $g_{m}^{\prime }$ ($g_{m1}^{\prime }+g_{m1A}^{\prime }$). Consequently, this trade-off leads to a degradation in the 2nd order input intercept point (IIP2), negatively impacting the linearity performance.

Fig. 8

Simulation result of $g_{m}^{\prime }$ in GPDK 90nm CMOS process, $(W/L)_{1} = 165/100$, $(W/L)_{1A} = 120/100$, $V_{ds} = 1$V

Fig. 9

Simulation result of $g_{m}^{\prime \prime }$ in GPDK 90nm CMOS process, $(W/L)_{1} = 165/100$, $(W/L)_{1A} = 120/100$, $V_{ds} = 1$ V

Limitations of using an auxiliary MOSFET in the weak inversion region in the Derivative Superposition (DS) method include (a) Limited frequency range of operation, (b) Inability to handle large input signals, and (c) Sensitivity to PVT variations (process, voltage, and temperature) for linearity improvement.

The Derivative Superposition (DS) technique has been employed in various literature [15, 22,23,24, 37, 38] to linearize the $g_{m1A}^{\prime \prime }$ of the CS transconductance stage MOSFET $M_{1}$, either on its own or in combination with other techniques.

3.2 Complementary derivative superposition (CDS)

Derivative superposition (DS) linearization approach to improve the IIP3 but degrade the IIP2 performance of the mixer. To address this issue, the auxiliary NMOS ($M_{1A}$) can be replaced with a PMOS ($M_{1P}$) in the Complementary Derivative Superposition (CDS) method [39] as shown in Fig. 10. Output current ($i_{RF}$) can be written as,

$$i_{RF}=(g_{m1} + g_{m1p})v_{gs}+ (g_{m1}^\prime - g_{m1p}^\prime )v_{gs}^2 + (g_{m1}^{\prime \prime } + g_{m1p}^{\prime \prime })v_{gs}^3$$

(7)

From Eq. 7, the total $g_{m}$ will increase to ($g_{m1}$ + $g_{m1p}$). $g_{m1}^{\prime }$ of $M_{1}$ and $g_{m1p}^{\prime }$ of $M_{1P}$ are added with opposite signs, resulting in an overall $g_{m}^{\prime }$ of zero, while $g_{m1}^{\prime \prime }$ of $M_{1}$ and $g_{m1p}^{\prime \prime }$ of $M_{1P}$ are subtracted with the same sign, resulting in a reduction in $g_{m}^{\prime }$, as shown in Figs. 11 and 12. A cancellation window for $g_{m}^{\prime \prime }$ is wider for DS compared to CDS. Therefore, the enhancement in IIP3 is not as substantial as that observed in Derivative Superposition (DS).

Fig. 10

Complementary derivative superposition technique

Fig. 11

Simulation result of $g_{m}^{\prime }$ in GPDK 90nm CMOS process, $(W/L)_{1}=165/100$, $(W/L)_{1A}=120/100$, $V_{ds} = 1$ V

Fig. 12

Simulation result of $g_{m}^{\prime \prime }$ in GPDK 90nm CMOS process, $(W/L)_{1}=165/100$, $(W/L)_{1A}=120/100$, $V_{ds} = 1$ V

In the Complementary DS (CDS) technique, the optimal biasing of $g_{m1}^{\prime }$ and $g_{m1}^{\prime \prime }$ does not coincide. Consequently, two options are available: $g_{m1}^{\prime \prime }$ and $g_{m1p}^{\prime \prime }$ can be matched to achieve a good 3rd order input intercept point (IIP3) while partially cancelling $g_{m1}^{\prime }$, and $g_{m1p}^{\prime }$ can be matched to attain the optimal 2nd order input intercept point (IIP2).

The CDS technique is used to linearize the transconductance stage of the down-conversion mixer, which is operated for Band-1 (3.1$-$4.8 GHz) of the UWB mixer [25]. In [26] and [27], various versions of CDS are discussed which can be used in the mixer to improve the IIP3 and IIP2. $g_{m1}^{\prime \prime }$ of the RF stage of an active mixer can be canceled by applying a voltage to the bulk terminal, called the Gate-Bulk Interaction Technique [40, 41].

3.3 Post distortion (PD)

The Post-distortion method, as compared to the DS method, employs an auxiliary MOSFET connected at the drain of the RF stage MOSFET. This auxiliary MOSFET is utilized to cancel out the $g_{m}^{\prime }$ and $g_{m1}^{\prime \prime }$ characteristics of the RF stage MOSFET ($M_{1}$) in mixers [33].

Figures 13 and 14 illustrate the implementation of CG and CS post-distortion, with MOSFETs $M_{1}$ and $M_{2}$ degenerated by resistance ($Z_{s}$). The increased parasitic capacitance reduces conversion gain ($G_{c}$) at higher frequencies, mainly due to Cgs of the LO MOSFET ($M_{3}$ - $M_{6}$) as shown in Fig. 3. To counteract the effects of parasitic capacitance at the source node of the switching stage and ensure a consistent conversion gain ($G_{c}$) across a wider frequency range, inductor $L_{1}$ (depicted in Fig. 13) and inductor $L_{2}$ (depicted in Fig. 14) are introduced between the LO and RF stages. Recent research, as reported in [42], proposes the utilization of Active Inductor (AI) instead of simple inductors, offering enhanced bandwidth.

The implementation of CG and CS post-distortion are shown in Figs. 13 and 14, where MOSFET $M_{1}$ and $M_{2}$ is degenerated by resistance ($R_s$). For CG implementation, current flowing through the $M_{1}$ and $M_{1Q}$ can be written as,

$$\begin{aligned} \begin{aligned} i_{RF}=G_{m1}v_{RF}+{G_{m1}^\prime }v_{RF}^2+{G_{m1}^{\prime \prime }}v_{RF}^3 \end{aligned} \end{aligned}$$

(8)

where,

$$\begin{aligned} G_{m1}= & {} \ \frac{g_{m1}}{1+g_{m1}Z_s} \end{aligned}$$

(9)

$$\begin{aligned} i_{1Q}= & {} g_{m1Q}v_{RF}+\ g_{m1Q}^\prime v_{RF}^2+g_{m1}^{\prime \prime }v_{RF}^3 \end{aligned}$$

(10)

$$i_{{RF}} = {\text{ }}i_{1} + i_{{1Q}} = \left( {G_{{m1}} + g_{{m1Q}} } \right)v_{{RF}} + {\text{ }}\left( {G_{{m1}}^{\prime } + g_{{m1Q}}^{\prime } } \right)v_{{RF}}^{2} + {\text{ }}\left( {G_{{m1}}^{{\prime \prime }} + g_{{m1Q}}^{{\prime \prime }} } \right)v_{{RF}}^{3}$$

(11)

$$\begin{aligned} IIP3= & {} \sqrt{\frac{4\ \left( G_{m1}+g_{m1Q}\right) }{3\ \left( G_{m1}^{\prime \prime }+g_{m1Q}^{\prime \prime }\right) }} \end{aligned}$$

(12)

By observing Eqs. 11 and 12, it becomes evident that the linearity (IIP3) can be enhanced by reducing the term ($g_{m1}^{\prime \prime }$ + $g_{m1Q}^{\prime \prime }$). To achieve this, proper biasing of the transistors ($M_{1}$) and ($M_{1Q}$) is required.

Fig. 13

Common Gate (CG) Post-distortion [33]

Fig. 14

Common Source (CS) Post-distortion [33]

However, the post-distortion (PD) method offers advancements in 2 key aspects:

• 1. The auxiliary MOSFET is connected to the output of the main MOSFET rather than directly to the input. This minimizes the impact on input matching, ensuring better overall performance.

• 2. All MOSFET operates in saturation, providing a more robust cancellation of distortions.

These advancements make the post-distortion method a more suitable technique for canceling out $g_{m1}^{\prime }$ and $g_{m1}^{\prime \prime }$ in the RF stage MOSFET ($M_{1}$). The post-distortion method involves operating both MOSFETs $M_{1}$ and $M_{1Q}$ in the saturation region, which results in no degradation of the conversion gain ($G_{c}$) and noise figure compared to the DS and CDS methods.

3.4 Noise/distortion cancellation

Noise is a crucial consideration in mixer design, with the Noise Figure (NF) often being relatively high. Various circuit topologies are employed to minimize both flicker [16] and white noise in CMOS mixers. In [43], a novel RF CMOS Gilbert mixer is proposed to enhance NF. This mixer utilizes a PMOS switching circuit with an inductor to sharpen switching transitions and reduce flicker noise at the switching stage. Additionally, in [24, 28,29,30,31, 44], circuit topologies are utilized to minimize RF stage noise in CMOS down-conversion mixers. The principle of noise cancellation is depicted in Fig. 15, with $R_{s}$ representing the source impedance. The concept of noise cancellation [45] involves the identification of two nodes (X and Y) in the RF stage. At these nodes, the signal exhibits opposite polarities, while the noise from the input transistor exhibits the same polarity. When nodes X and Y satisfy this condition, their voltages can be appropriately scaled and combined, resulting in the addition of signal components and cancellation of noise components.

Two topologies can be utilized for noise cancellation in the RF stage of the Mixer: (1) Common Gate (CG)-Common Source (CS) topology (2) Common Source (CS) topology with feedback (resistive).

Fig. 15

Conceptual representation of noise cancellation technique

Fig. 16

CG- CS approach differential output [30]

Fig. 17

CG-CS approach single ended output [31]

Fig. 18

CS Resistive feedback [29]

3.4.1 CG-CS topology

The CG-CS approach offers two possible output configurations, namely the differential output [30] and the single-ended output [31, 46], as illustrated in Figs. 16 and 17 respectively. The utilization of a differential output in the differential approach eliminates the requirement for a balun at the input of the RF stage. However, there are various trade-offs to consider among gain, IIP3 (3^rd order intercept point), and noise figure. To mitigate these trade-offs, one can introduce an additional NMOS ($M_{1F}$) to convert the differential output to single-ended output as shown in Fig. 17. This conversion helps in eliminating the trade-offs associated with the differential approach.

In the CG-CS noise cancellation approach, the input CG MOSFET ($M_{1E}$) generates a noise voltage with opposite polarity at nodes X and Y, while the input signal remains in phase, as depicted in Figs. 15 and 16 respectively. To combine the input signal and effectively cancel the noise (channel, thermal) and distortion generated by the input MOSFET ($M_{1E}$) at the output, it is necessary for the gain of the CG stage ($M_{1E}$) and the CS stage ($M_{1}$) to be equal. This condition results in the Noise Cancellation Condition for differential output as,

$$\begin{aligned} \begin{aligned} g_{m1E}R_1=\ \ g_{m1}R_2 \end{aligned} \end{aligned}$$

(13)

For single-ended output,

$$\begin{aligned} \begin{aligned} g_{m1F}R_1=\ \ g_{m1}R_S \end{aligned} \end{aligned}$$

(14)

In the CG-CS topology, the RF signal is applied to the source of the CG MOSFET ($M_{1E}$). The impedance seen at the source of ($M_{1E}$) is approximately $\left( {\frac{1}{{g_{{m1E}} }}} \right)$, allowing for the straightforward achievement of wideband input matching by appropriately setting the value of ($g_{m1E}$). Limitations:

• 1. The inclusion of an additional MOSFET ($M_{1F}$) in the CG-CS single-ended output configuration of Fig. 17 leads to increased noise compared to the CG-CS differential configuration.

• 2. While the noise and distortion originating from ($M_{1E}$) are effectively eliminated by the noise cancellation (NC) methods, it is important to note that the presence of ($M_{1F}$) and ($M_{1}$) can still introduce residual noise and distortion. These residual factors can potentially impact the linearity performance of the mixer.

3.4.2 CS-resistive feedback topology

This approach, as shown in Fig. 18, replaces the CG input MOSFET ($M_{1E}$) with a CS MOSFET ($M_{1C}$), distinguishing it from the CG-CS topology. As discussed in the CG-CS topology, the noise and RF signal from the input MOSFET ($M_{1C}$) generate opposite polarity noise voltage at Node X and an in-phase RF signal at Node Y. Noise cancellation condition for CS-Resistive feedback topology can be written as,

$$\begin{aligned} \begin{aligned} g_{m1}R_S=\ \ g_{m1D}\left( R_S+R_F\right) \end{aligned} \end{aligned}$$

(15)

Fig. 19

Modified noise cancellation approach [29]

This approach suffers from insufficient output impedance, making it unsuitable for direct integration as the RF stage in the down-conversion mixer. However, in [29], an enhanced resistive feedback noise cancellation approach is presented. This modification involves substituting the source follower ($M_{1D}$) with a common-gate (CG) amplifier and replacing the input RF stage with a complementary resistive feedback amplifier ($M_{2NC}$, $M_{2PC}$ and $R_F$). Additionally, the output is converted into a complementary output stage, as depicted in Fig. 19. This modification results in additional feed-forward signal amplification, leading to increased gain and reduced noise in the circuit. Furthermore, the modified approach exhibits a desirable characteristic of high output impedance, making it well-suited for use as an RF stage in the down-conversion mixer. The noise cancellation condition for Fig. 19 can be modified as given in [29].

$$\begin{aligned} \begin{aligned} \left( g_{m1N}+g_{m1P}\right) R_S=\ \ g_{m1D}\left( R_S+R_F\right) \end{aligned} \end{aligned}$$

(16)

where, $g_{m1N}$, $g_{m1P}$, $g_{m1D}$ are the transconductance of MOSFET $M_{1N}$, $M_{1P}$ and $M_{1D}$ respectively. The output complementary stage allows the cancellation of distortion from $M_{1N}$ and $M_{1D}$ effectively by $M_{1P}$, which is biased in the weak inversion region and carefully optimized around the sweet spot to minimize $g_{m1N}^{\prime \prime }$ and $g_{m1D}^{\prime \prime }$. This optimization leads to a noticeable improvement in IIP3. Furthermore, to remove the impact of second-order interaction on IIP3, complementary configurations are proposed in [28]. The CG-CS noise cancellation approach for the RF stage in a mixer is superior to the CS-Resistive approach, especially in situations where wideband (WB) input matching, higher conversion gain ($G_{c}$), and low Noise Figure (NF) are required.

3.5 Current injection

The methods mentioned above, such as noise cancellation (NC), post-distortion (PD), CDS (complementary DS), and DS (Derivative Superposition), are utilized to eliminate $g_{m1}'$ and $g_{m1}''$ in the RF STAGE $M_{1}$, resulting in an enhancement of IIP3.

Moreover, as explained in Sect. 2.2, the mixer’s IIP3 is affected by the time interval ($\left( \Delta \right)$) when one of the switching MOSFETs enters the triode region, leading to deterioration in the linearity of the mixer, as depicted in Fig. 6. To prevent the switching MOSFETs from entering the triode region, it is necessary to maintain a sufficient voltage at the drain node of $M_{3}$ and $M_{4}$. To accomplish this, both static and dynamic current injection approaches have been proposed in [17], as illustrated in Figs. 20 and 21.

Minimum node voltages at X and Y can be written as,

$$\begin{aligned} \begin{aligned} V_{X,Y,(min)}=V_{ov1}+\left( 1+\frac{\sqrt{2}}{2}\right) V_{ov\ 3,4} \end{aligned} \end{aligned}$$

(17)

where, $V_{ovn}$ = Overdrive voltage of MOSFET $M_{n}$.(n = 1,2,3,4)

$$\begin{aligned} \begin{aligned} {Conversion Gain}_{max\ }=\ \frac{2}{\pi }\frac{V_{Rmax}}{V_{ov1}} \end{aligned} \end{aligned}$$

(18)

Fig. 20

Static current injection method [17]

Fig. 21

Dynamic current injection method [17]

The implementation of static current injection involves the connection of PMOS transistors $M_{7}$ and $M_{8}$ across the load resistor ($R_{L}$), as depicted in Fig. 20. To ensure that the external current sources ($M_{7}$ and $M_{8}$) remain in saturation during LO zero crossings, it is necessary to maintain a sufficient voltage across the load resistor.

$$\begin{aligned} \begin{aligned} V_{Rmaximum}={Max\left( V_{R_{L}}\right) =V}_{DD}-V_{X,Y,Min} \end{aligned} \end{aligned}$$

(19)

Fig. 22

Concept of current bleeding

The static current injection method [17] involves the continuous injection of a constant current throughout the entire duration of the LO signal. While this approach provides only a limited improvement in conversion gain, it helps mitigate signal compression at the output. To further enhance conversion gain and reduce signal compression, dynamic current injection is utilized. In this method, the current is injected at the nodes X and Y using a PMOS ($M_{7}$ - $M_{10}$) cross-coupled pair, as depicted in Fig. 21. Additionally, dynamic current injection eliminates the voltage across the $R_{L}$ at the zero crossing LO signal.

Furthermore, the current bleeding/Injection method also enhances flicker (1/f) noise performance, which involves reducing the current in the switching stage to decrease the height of noise pulses [18]. This reduction is achieved by introducing additional bias current ($I_{bld}$) at the source node of the switching stage, as illustrated in Fig. 22. The current bleeding technique aims to lower the bias current of the LO switches. However, this action leads to an increase in the impedance of the LO switches as observed from the RF stage. Furthermore, RF leakage current enters the bleeding circuit, resulting in reduced conversion gain ($G_{c}$) and allowing more RF current to be diverted by the parasitic capacitance ($C_{p}$) at the node between the LO switches and the RF transconductance stage. Minimizing $C_{p}$ is crucial for indirectly reducing flicker noise [16]. To achieve this, using smaller device sizes for the LO switches is appropriate, although it may increase intrinsic flicker (1/f) noise. Another proposed technique, dynamic current bleeding, enhances flicker-noise performance by injecting a dynamic current equal to the bias current of the LO switches only during LO switching events [16].

4 Research scope, challenges and future direction

4.1 Research Scope and Challenges

In the field of communication technology, Ultra-Wideband (UWB) devices have experienced rapid growth across diverse domains, including medical applications, short-range distance communication, positional tracking, and beyond [2, 3, 15, 21]. The extensive adoption of UWB underscores the need for continuous advancements in downconversion mixer research, offering both opportunities for future developments and significant challenges.

• (A) Challenges in mixer design for specific applications: Creating a down-conversion mixer tailored for a specific job is quite a challenge. It needs to perform well in areas like conversion gain ($G_{c}$), Noise Figure (NF), Linearity (IIP3, IIP2, P1dB), Port-to-Port Isolation, and more [10]. Achieving this optimal performance depends on how well we design and optimize CMOS mixers. However, this task comes with its share of difficulties, such as managing extra flicker noise, reducing LO port leakage, controlling high power consumption, and solving other tricky problems. Designing CMOS mixers is like solving a complex puzzle with many different elements that need to be just right. It’s not just about making something that works; it’s about making something that works well while navigating through all these challenges [10].

• (B) Growing demand for bandwidth and research focus: In recent years, the surge in demand for expanded bandwidth has propelled intensified research efforts in multiband mixers [10, 47]. The exploration of Multiband or Wideband mixers exposes challenges associated with nonlinearity stemming from neighboring bands. Consequently, the pursuit of enhanced linearity, particularly concerning 2nd and 3rd order non-linearity, has become a noteworthy and actively researched domain in the realm of multiband mixers.

• (C) Linearization techniques and ongoing challenges: This review article delves into various linearization techniques, providing a thorough analysis and detailed comparisons. Table 3 encapsulates a comprehensive overview of reported linearization techniques for down-conversion mixers. Notably, challenges persist in achieving an optimal balance. The Capacitive feedback approach [37] achieves an Average Value of IIP3 of 20.5 dBm, but at the expense of noise performance (NF = 16.9 dB). Despite advancements, challenges linger, as evidenced by higher Noise Figure (NF) ranging from 11 to 14 dB in methods like CDS and DS/MGTR [15, 22, 23].

Table 3 Comparison of different linearization methods for the mixer

4.2 Future direction

• (a) Optimizing down-conversion mixer parameters:

  • Designing a down-conversion mixer for a specific application with optimal parameters like conversion gain ($G_{c}$), Noise Figure (NF), Linearity (IIP3, IIP2, P1dB), Port-to-Port Isolation, and more [10]. Using gm/ID methods for down-conversion mixers [48, 49] to optimize CMOS mixers.

• (b) Addressing challenges through innovative techniques:

  • Methods like noise cancellation have been applied in the context of mixer design [31, 28, 29]. Although these strategies show positive results in aspects such as IIP3, conversion gain ($G_{c}$), and noise figure (NF), obstacles still exist. The challenge lies in achieving simultaneous enhancements in both IIP3 and IIP2 at the RF stage while addressing signal compression at the IF stage, presenting a substantial hurdle. This emphasizes the possibility of future improvements to enhance the overall performance across the Wideband (WB) spectrum.

• (c) Incorporating innovative techniques from LNA architectures:

  • Incorporating inventive methodologies from various Low-Noise Amplifier (LNA) architectures into mixers has the potential to augment performance. The utilization of various gain (gm) boosting techniques at the Common Gate (CG) stage [29, 30] can diminish the matching inductor size ($L_{in}$) and enhance matching. The integration of this improved LNA with a down-conversion mixer shows promise for enhancing linearity at the RF stage. Exploring additional techniques like inductive peaking [31, 50], active inductors [42], bulk LO injection, etc., in mixer design aims to widen the bandwidth. It’s essential to acknowledge that these methods may introduce additional parasitic capacitance. Subsequent research in this field could focus on layout optimizations to further refine and propel these concepts.

5 Conclusion

This article has explored various linearity improvement methods for CMOS Active current commutating mixers. The investigation involved considering trade-offs between linearity, conversion gain, and power dissipation. The use of DS and CDS techniques proved effective in enhancing the linearity of the RF stage ($g_{m}^{\prime }$ and $g_{m}^{\prime \prime }$), but it led to a degradation in the Noise Figure. To further improve IIP3, IIP2, and $P_{1}dB$ in the RF stage, noise cancellation techniques in combination with linearization methods such as DS, CDS, or post-distortion can be applied simultaneously. Additionally, dynamic current injection can be implemented to enhance the linearity of the switching stage. By employing linearization techniques at both the switching and RF stages of the mixer, better overall linearization performance can be achieved. These findings contribute to advancing linearity techniques for CMOS Active current commutating mixers and guide the design of high-performance and linear mixers in practical wideband applications.