Integrity of ultrathin gate oxides with different oxide thickness, substrate wafers and metallic contaminations

Abstract.

The integrity of ultrathin gate oxides was investigated as a function of polished and epitaxial wafer surfaces with various gettering sites. After intentional contamination of wafers with 1×10¹¹ atoms/cm² and 5×10¹² atoms/cm² Cu and Ni by a spin-on technique of high reproducibility, we performed 0.18-μm low-thermal-budget CMOS process runs. Thermal oxides were grown with various gate oxides in the range of 5–17 nm. After a MOS-capacitor fabrication we applied a ramped current-density test to study the gate-oxide integrity. Generally, thinner gate oxides exhibited a much more robust behavior than thicker oxides. The gate-oxide integrity was strongly influenced by different gettering sites. Although a higher Ni contamination led to a higher number of gate-oxide failures, Cu contamination exhibited a higher impact on the gate-oxide integrity than Ni.