Reliability Implications of Fast and Slow Degradation Processes in High-k Gate Stacks

Abstract

Aggressive transistor scaling to achieve better chip functionality is driving the introduction of high-k dielectric materials into traditional device gate stacks. These advanced gate stacks are multilayer structures, the materials of which may strongly interact during high temperature processing, generating structural defects in the layers. Such complex structures pose new challenges in interpreting electrical measurements, which are sensitive to even extremely small concentrations of electrically active defects. A high density of pre-existing defects and defect precursors is shown to give rise to both fast and slow instabilities in the device characteristics, some of which may be reversible while others cause unrecoverable dielectric degradation. In this chapter, we focus on the reliability implications of instabilities associated with pre-existing structural defects in both the high-k film and the interfacial layer of gate oxide stacks subjected to a variety of reliability tests.