Abstract
In this paper, we presented a low-power, less area architecture of S-Box used in advanced encryption standard (AES) using programmable cellular automata (PCA). The proposed architecture performance in terms of security is evaluated using cryptographic properties such as nonlinearity, input/output entropy, correlation immunity bias, balancedness property, strict avalanche criterion, and it is found that the proposed method is secure enough for cryptography applications. The proposed architecture of AES with PCA-based S-Box is implemented on ASIC using TSMC 0.18-\({\upmu }\)m and UMC 0.13-\({\upmu }\)m CMOS technology libraries. Simulation studies show that the proposed architecture has average energy consumption of 58.702 nJ, power dissipation of 3.259 mW, area of 0.184 mm\(^2\), for TSMC 0.18-\({\upmu }\)m at 13.69 MHz and energy consumption of 18.275 nJ, power dissipation of 1.026 mW, area of 0.069 \({\upmu m}^{2}\) for UMC 0.13-\({\upmu }\)m at 13.69 MHz. The proposed architecture shows reduction in power dissipation by 83% and in energy consumption by 10% compared to the best classical S-Box and composite field arithmetic-based S-Box for AES algorithm. The S-Box using PCA is more flexible and dynamic in nature with low power, lesser energy consumption area and hence suitable for wireless body area network applications.
Similar content being viewed by others
References
Advanced Encryption Standard (AES),Federal Information Processing Standards Publication 197 Std., (2001)
A. Bechtsoudis, N. Sklavos, Side channel attacks cryptanalysis against block ciphers based on FPGA devices. in Proceedings of 2010 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2010), pp. 460–461
J.A. Clark, J.L. Jacob, S. Stepney, The design of S-boxes by simulated annealing. New Gener. Comput. 23(3), 219–231 (2005)
Y. Eslami, A. Sheikholeslami, P.G. Gulak, S. Masui, K. Mukaida, An area-efficient universal cryptography processor for smart cards. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 14(1), 43–56 (2006)
M. Feldhofer, S. Dominikus, J. Wolkerstorfer, Strong authentication for RFID systems using the AES algorithm. in Cryptographic Hardware and Embedded Systems-CHES 2004, ser. Lecture Notes in Computer Science Vol. 3156 (Springer, Berlin, Heidelberg, 2004), pp. 357–370
B.R. Gangadari, S. Ahamed, R. Mahapatra, R. Sinha, Design of cryptographically secure AES S-box using cellular automata. in Proceedings of International Conference on Electrical, Electronics, Signals, Communication and Optimization (EESCO), 2015 (2015), pp. 1–6
T. Good, M. Benaissa, Very small FPGA application-specific instruction processor for AES. IEEE Trans. Circuits Syst I Regul. Pap. 53(7), 1477–1486 (2006)
A. Hodjat, I. Verbauwhede, Area-throughput trade-offs for fully pipelined 30 to 70 Gbits/s AES processors. IEEE Trans. Comput. 55(4), 366–372 (2006)
I. Hussain, T. Shah, M.A. Gondal, W.A. Khan, Construction of cryptographically strong 8\(\times \)8 S-boxes. World Appl. Sci. J. 13(11), 2389–2395 (2011)
IEEE Standard for Local and metropolitan area networks—Part 15.6: Wireless Body Area Networks, Std., (2012)
H. Kapoor, G.B. Rao, S. Arshi, G. Trivedi, A security framework for NoC using authenticated encryption and session keys. Circuits Syst. Signal Process. 32(6), 2605–2622 (2013)
J.P. Kaps, B. Sunar, Energy comparison of AES and SHA-1 for ubiquitous computing. in Emerging Directions in Embedded and Ubiquitous Computing, ser. Lecture Notes in Computer Science Vol. 4097 (Springer, Berlin, Heidelberg, 2006) pp. 372–381
M. Kim, J. Ryou, Y. Choi, S. Jun, Low power AES hardware architecture for radio frequency identification. in Advances in Information and Computer Security, IWSEC 2006. ser. Lecture Notes in Computer Science Vol. 4266 (Springer, Berlin, Heidelberg, 2006), pp. 353–363
S. Kumar, V.K. Sharma, K.K. Mahapatra, An improved VLSI architecture of S-box for AES encryption. in Proceedings of 2013 International Conference on Communication Systems and Network Technologies (CSNT) (2013), pp. 753–756
H. Kuo, I. Verbauwhede, Architectural optimization for a 1.82Gbits\(/\)sec VLSI implementation of the AES Rijndael algorithm. in Cryptographic Hardware and Embedded Systems CHES 2001, ser. Lecture Notes in Computer Science Vol. 2162 (Springer, Berlin, Heidelberg, 2001), pp. 51–64
H. Li, Efficient and flexible architecture for AES. IEEE Proc. Circuits Devices Syst. 153(6), 533–538 (2006)
W. Millan, How to improve the nonlinearity of Bijective S-boxes. in Third Australasian Conference on Information Security and Privacy.ser. ACISP ’98. (Springer-Verlag, London, 1998), pp. 181–192
S. Morioka, A. Satoh, An optimized S-box circuit architecture for low power AES design. in Cryptographic Hardware and Embedded Systems-CHES 2002, ser. Lecture Notes in Computer Science Vol. 2523 (Springer, Berlin, Heidelberg, 2003), pp. 172–186
S. Morioka, A. Satoh, A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(7), 686–691 (2004)
S. Nandi, B.K. Kar, P.P. Chaudhuri, Theory and application of cellular automata in cryptography. IEEE Trans. Comput. 43(12), 1346–1357 (1994)
National Institute of Standards and Technology, FIPS PUB 46-3: Data Encryption Standard (DES), (Oct. 1999), super-sedes FIPS, 46-2
N. Nedjah, L.d M. Mourelle, Designing substitution boxes for secure ciphers. Int. J. Innov. Comput. Appl. 1(1), 86–91 (2007)
A. Satoh, S. Morioka, K. Takano, S. Munetoh, A compact Rijndael hardware architecture, with S-Box optimization. in Advances in Cryptology, ASIACRYPT. Lecture Notes in Computer Science Vol. 2248 (Springer, Berlin, Heidelberg, 2001), pp. 239–254
T.M. Sharma, R. Thilagavathy, Performance analysis of advanced encryption standard for low power and area applications. in Proceedings of 2013 IEEE Conference on Information Communication Technologies (ICT) (2013), pp. 967–972
M. Szaban, F. Seredynski, CA-based generator of S-boxes for cryptography use. in Proceedings of 2010 IEEE International Symposium on Parallel Distributed Processing, Workshops and Phd Forum (IPDPSW) (2010), pp. 1–8
M. Szaban, F. Seredynski, Dynamic cellular automata-based S-Boxes. in 13th International Conference Computer Aided Systems Theory-EUROCAST 2011. ser. Lecture Notes in Computer Science Vol. 6927 (Springer, Berlin, Heidelberg, 2012) pp. 184–191
X. Zhang, K.K. Parhi, High-speed VLSI architectures for the AES algorithm. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 12(9), 957–967 (2004)
X. Zhang, K.K. Parhi, On the optimum constructions of composite field for the AES algorithm. IEEE Trans. Circuits Syst. II Express Briefs 53(10), 1153–1157 (2006)
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Gangadari, B.R., Ahamed, S.R. Programmable Cellular Automata-Based Low-Power Architecture to S-Box : An Application to WBAN. Circuits Syst Signal Process 37, 1116–1133 (2018). https://doi.org/10.1007/s00034-017-0592-8
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s00034-017-0592-8