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A Reduced-sp-\(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm

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Abstract

A low-power, high-speed \(4\times 4\) multiplier using Dadda algorithm is proposed. The full adder blocks used in this multiplier have been designed using reduced-split precharge-data driven dynamic sum logic. Flip flops used in the pipeline registers have been designed to increase input signal noise margin, resulting in the minimization of output signal glitches. The multiplier circuit is implemented in 1P-9M Low-K UMC 90nm CMOS process technology. Post-layout simulations are carried out using Cadence Virtuoso. The proposed multiplier operates at a clock frequency of 3.5 GHz, with an average dynamic power consumption of 1.096 mW at a temperature of \(27\,^{\circ }\hbox {C}\) and 1 V supply voltage and occupies a chip area of \(76\,\upmu \hbox {m}\times 102\,\upmu \hbox {m}\).

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Authors and Affiliations

  1. Department of Electrical Engineering, University of Engineering and Technology, Taxila, Pakistan

    Zain Shabbir, Anas Razzaq Ghumman & Shabbir Majeed Chaudhry

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  1. Zain Shabbir
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  2. Anas Razzaq Ghumman
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  3. Shabbir Majeed Chaudhry
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Correspondence to Shabbir Majeed Chaudhry.

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Shabbir, Z., Ghumman, A.R. & Chaudhry, S.M. A Reduced-sp-\(\hbox {D3L}_{\mathrm{sum}}\) Adder-Based High Frequency \(4\times 4\) Bit Multiplier Using Dadda Algorithm. Circuits Syst Signal Process 35, 3113–3134 (2016). https://doi.org/10.1007/s00034-015-0201-7

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