Lower-part approximate multi-bit adders for low-power DSP

Abstract

This paper presents seven novel ‘Lower-part approximate multi-bit adders’ (LAMAs). The LAMAs namely lower-part NOR, AND, NAND, XOR, XNOR, ‘lower-part constant-1 adder’ (LCONE), and ‘lower-part constant-0 adder’ (LCZERO) are derived based on the hardware architecture of ‘Lower-part OR adder’ (LOA). The performance metrics of these proposed adders are compared with LOA, lower-part NOT1, and lower-part NOT2. For a fair comparison an 8-bit LAMA is designed using Verilog ‘hardware-description-langauge’ (HDL). The 8-bit LAMA is divided into two equal segments namely ‘most-significant-bit’ (MSB) and ‘least-significant-bit’ (LSB) adders. The MSB adder is designed using ‘ripple carry adder’ (RCA) and LSB adder is designed using LAMA. To assess the performance of the proposed adders, all the ten adders are compared in terms of ‘design metrics’(DMs) such as power, delay, ‘power-delay-product’ (PDP), and area. To extract the DMs for performance comparison, all the ten adders have been designed using a Verilog ‘register-transfer-level’ (RTL) code. The RTL coded adders are then synthesized using Cadences’ ‘RTL-Compiler’(RC) tool, using 180 nm standard cell library. The synthesis results show that proposed LAMAs have better DMs compared to conventional LOA. Further to demonstrate the application of LAMAs, an image addition is performed using standard test images and their respective ‘peak-signal-to-noise-ratio’(PSNR) and ‘structural similarity index’ (SSIM) have also been extracted. The PSNR values of the proposed LAMAs are found to be better than the reported LAMAs.