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Sulla sintesi di reti NAND o nor a molti livelli

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Summary

Some authors have proved that a minimal two-level NAND or NOR network can be obtained by the convetional procedures for determining minimal normal forms. But when either the complements of some input variables are not available or the gates have a limited number of inputs, the two-level synthesis is generally impossible; and no procedure has been described for the minimal sunthesis of networks having more than two levels of gates.

In this paper some new procedures are described for the synthesis of NAND or NOR networks having more than two levels of gates.

In the first sections the properties are briefly described, by which a NAND or NOR expression is equivalent to a conventional expression containing only the AND and OR operators; also, the problem of determining a minimal two-level NAND or NOR network is summarized.

Then the synthesis of three-level NAND or NOR networks is considered, in case that both the true and complemented values of input variables are available, and the gates can have an unlimited number of inputs (condition 1). A new procedure is described which makes it possible to find one of the minimal NAND or NOR networks, having a tree-shaped structure, and which gives also quasi-minimal solutions for the general case in which the output of a gate can be connected to the inputs of more than one gate of the next level. The procedure derives from the methods described in a preceding paper by the present author for determining the minimal «sums of products of sums» of an assigned function; but some properties and the particular definition of cost make it possible to apply a computation technique, which simplifies this problem considerably.

Then the synthesis problem is considered when the gates can have an unlimited number of inputs but the complements of some of the input variables are not available (condition 2). In this case the two-level synthesis is generally impossible (a simple necessary and sufficient condition for a two-level solution to exist is proved); on the contrary, a three-level NAND or NOR network always exists, which implements the assigned function. This network can be determined with the procedure which has been described for determining the minimal three-level networks in condition 1, but the new conditions simplify the problem and a remarkable reduction of the computation work is possible.

Lastly the following cases are considered:

  1. a)

    both the true and the complemented values of the input variables are available, but the gates have a limited number of inputs (condition 3);

  2. b)

    the complements of some input variables are not available and the gates have a limited number of inputs (condition 4).

In these cases a two- or a three-level synthesis may be impossible, but one can always verify whether a two- or a three-level network implementing the assigned function exists. However a simple procedure is described, which always makes it possible to find a quasi-minimal solution characterized by more than three levels of gates.

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Bibliografia Sintesi di reti NAND e NOR

  1. L. Dadda, “Le operazioni di Pierce e di Sheffer”, Res. dell'Ist. Lombardo, 1959, pag. 565.

  2. L. Dadda, “Sulla nozione di dualità fra funzioni di commutazione”, Res. dell'Ist. Lombardo, 1959, pag. 586.

  3. J.M. Boswell., “NOR Logic”, Instruments and Control Systems,33, (1960), 1523–1525.

    Google Scholar 

  4. N. T. Grisamore, L. S. Rotola andG. U. Uyehara, “Logical design using the stroke function”, IRE Trans. on El. Comp.,EC-7, (1958), 181–183.

    Google Scholar 

  5. R. B. Hurley, “Exhaustive Boolean expressions”, El. Equip. Engrg,8, (1960), 86–87.

    Google Scholar 

  6. R. B. Hurley, “Transistor logic circuits”, John Wiley and Sons, Inc. New York, N. Y.; 1961.

    MATH  Google Scholar 

  7. P. Kellet, “The Elliott Sheffer stroke static switching system”, El. Engrg.,32, (1960), 534–539.

    Google Scholar 

  8. G. A. Maley, “Simplifying switching circuits with Boolean algebra”, Electro-Tech.,67, (1961), 101–106.

    Google Scholar 

  9. G. A. Maley andJ. Earle, “The Logical Design of Transistor Digital Computers”, Prentice-Hall, Inc., New York, N. Y., 1963.

    Google Scholar 

  10. W. D. Rowe, “The transistor NOR Circuit”, 1957 IRE Wescon Convention Record,1, pt. 4, (1957), 231–245.

    Google Scholar 

  11. H. M. Sheffer, “A set of five indipendent postulates for Boolean algebras”, Trans. Am. Math. Soc.,14 (1913), 481–488.

    Article  MathSciNet  MATH  Google Scholar 

  12. P. N. Sherer, “Logic design with NOR gates and NAND gates”, Elec. Design News,8, (1963), 96–103.

    Google Scholar 

Procedimenti classici di semplificazione delle funzioni logiche

  1. W. V. Quine, “The problem of simplifying truth functions”, Amer. Math. Mon.,59, (1952), 521–531.

    Article  MATH  MathSciNet  Google Scholar 

  2. C. E. Shannon, “A symbolic analysis of relay and switching circuits”, Trans. AIEE,57, (1938), 713–723.

    Google Scholar 

  3. A. Nakasima andM. Hanzawa, “The theory of equivalent transformation of simple partial paths in relay circuits”, J. Inst. Elec. Comm. Engrs. (Japan), 1936–1938.

  4. M. J. Gazale, “Irredundant disjunctive and conjunctive forms of a Boolean function”, I. B. M. J. Res. and Dev.,1, (1957), 171–176.

    Article  Google Scholar 

  5. E. M. McCluskey, “Minimization of Boolean functions”, Bell Sys. Tech. J.,35, (1956), 1417–1444.

    MathSciNet  Google Scholar 

  6. S. R. Petrick, “On the Minimization of Boolean Functions”, presentato al Symp. on Switch. Alg. ICIP, Paris, 1959.

  7. Harvard Computation Lab., “Annals of the Computation Laboratoyr”, in “Synthesis of El. Comp. and Control Circ.”, Harvard Univ. Press, Cambridge, Mass.,27; 1951.

    Google Scholar 

  8. E. W. Veitch, “A chart method for simplifying truth functions”, Proc. Assoc. Comp. Mach., Richard Rimbach Ass., Pittsburg, pp. 127–133; 1952.

  9. M. Karnaugh, “The map method for synthesis of combinational logic circuits”, Trans. AIEE Commun. and El., pt. I, 72.

  10. B. Harris, “An algorithm for determining minimal representations of a logic function”, IRE Trans. on El. Comp.,EC-6, (1957), 103–108.

    Google Scholar 

  11. M. Phister, “Logical design of digital computers”, J. Wiley and Sons, New York; 1958.

    MATH  Google Scholar 

  12. S. H. Caldwell, “Switching Circuits and Logicla Design”, J. Wiley and Sons, New York; 1958.

    Google Scholar 

La determinazione delle espressioni minime del terzo ordine

  1. Shreeram Abhyankar, “Minimal Sum of Products of Sums Expressions of Boolean Functions”, IRE Trans. on El. Comp.,EC-7, (1958), 268–276.

    Google Scholar 

  2. Shreeram Abhyankar, “Absolute Minimal Expressions of Boolean Fucntions”, IRE Trans. on El. Comp.,EC-8, (1959), 3–8.

    Google Scholar 

  3. A. R. Meo, “On the minimal third order Expression of a Boolean Function”, Proc. AIEE of the Third Ann. Symp. on Switch. Circ Th. and Log. Design (Chicago 7–12 Octobre 1962), New York, N. Y., 1962.

  4. E. L. Lawler, “Minimal Boolean Expressions with More than two Levels of Sums and Products”, Proc. AIEE of the Third Ann. Symp. on Switch. Circ. Th. and Log. Design (Chicago 7–12 Ottobre, 1962), New York, N. Y., 1962.

  5. A. R. Meo, “The determination of the minimal TANT networks”, Proc. of the Second Allerton Conf. on Circ. and Syst. Th., Settembre 1964.

La regola dei “consensus”

  1. W. V. Quine, “A way to simplify truth functions”, Amer. Math. Mant.,62, (1955) 627–631.

    Article  MATH  MathSciNet  Google Scholar 

  2. W. V. Quine, “On cores and prime implicants of truth functions”, Amer. Math. Mont.,66, (1959), 755–760.

    Article  MATH  MathSciNet  Google Scholar 

  3. T. H. Mott, “An Algorithm for Determining Minimal Forms of an Incomplete Truth Function”, art. CP 59-1123 presentato al AIEE Fall General Meeting, Chicago; Ottobre 1959.

  4. T. H. Mott, “Determination of the Irredundant Normal Forms of a Truth Function by Iterated Consensus of the Prime Implicants”, IRE Trans. on El. Comp.EC-9 (1960), 245–252.

    MathSciNet  Google Scholar 

  5. J. P. Roth, “Algebraic topological methods in synthesis”, proc. of an Int. Symp. on the Th. of Switch., (2–5 Aprile 1957) XXXIX ot Comp. Labor, of Harvard Univ., 57–73; 1959.

  6. A. R. Meo, “Un procedimento di semplificazione delle funzioni logiche”, Alta Frequenza,31, n. 7, (1962), 452–457.

    Google Scholar 

II metodo dei tre stadi

  1. A. R. Meo, “The determination of the ps prime implicants of a switching functions”, in corso di pnbblicazione.

Metodi topologici di sintesi

  1. R. H. Urbano eR. R. Mueller, “A topological method for the determination of the minimal forms of a Boolean function”, IRE Trans. on El Comp.,EC-5, (1956), 126–132.

    Google Scholar 

  2. J. P. Roth “Algebraic topologicla methods for the synthesis of switching systems in n variables”, Inst. for Advances Study, Princeton, N. J.,ECP 56-02, (1956).

    Google Scholar 

Strutture NAND o NOR tipo RTL

  1. J. Alman, P. Phipps andD. Wilson, “Design of a basic computer building block”, Proc. Western Joint Comp. Conf. (1957), 110–114.

  2. R. H. Beeson, “Transistor resistor logic (TRL) circuit design considerations of the Fairchild 2N706 and 2N708 transistors”, “Fairchild Application Note APP-15/2”, 1961.

  3. S. C. Chao, “Complementary resistor-transistor logic circuits”, Electronics,34, (1961), 47–52.

    Google Scholar 

  4. S. C. Chao, “Generalized RTL circuits-supplementary”, IRE Trans. on El. Comp.,EC-9, Settembre (1960), 371–372.

    Google Scholar 

  5. J. G. Curtis, “How important are resistor tolerances?”, El. Design,11, (1963), 44–49.

    Google Scholar 

  6. W. J. Dunnet, E. P. Auger andA. C. Scott, “Analysis of transistor-resistor logic circuit propagation delay”, Sylvania Tech. Rev.,12, (1959), 123–131.

    Google Scholar 

  7. R. B. Hurley, “Operation and logic of resistor-transistor switching circuits”, Electronic Equipment Engrg.,8, (1960), 61–63.

    Google Scholar 

  8. J. Luecke, “Silicon transistor-resistor logic circuits”, Elec. Manufacturing,66, (1960), 113–115.

    Google Scholar 

  9. M. Marcovits andE. Seif, “Analytical design of resistor coupled transistor logic circuits”, IRE Trans. on El. Comp.,EC-7, (1958), 109–119.

    Google Scholar 

  10. E. Nussbaum, E. A. Irland, andC. E. Young, “Statistical analysis of logic circuit performance in digital systems”, Proc. IRE,49, (1961), 236–244.

    Article  MathSciNet  Google Scholar 

  11. Q. W. Simkis, “Transistor resistor logic”, Semincon. Prod.,2, (1959), 34–38.

    Google Scholar 

  12. W. R. Smith, “Resistor-transistor-backward diode nanosecond logic”, Semicond. Prod.,6, (1963), 17–23.

    Google Scholar 

  13. W. J. Wray Jr., “DC design of resistance coupled transistor logic circuits”, IRE Trans. on Circuit Theory,CT-6, (1959), 304–310.

    Google Scholar 

  14. H. S. Yorke, S. A. Butler andW. G. Strohm, “NOR logic (RTL)design with Si transistors”, Elec. Design News,8, (1963), 102–103.

    Google Scholar 

Strutture NAND o NOR tipo RCTL

  1. P. L. Cloot, “A basic transistor circuit for the construction of digital-computing systems”, Proc. IEE,105 B, (1958), 213–220.

    Google Scholar 

  2. P. L. Cloot andG. E. Jackson, “The construction of digital computing system from a basic transistor circuit”, El. Engrg.,32, (1960), 37–43.

    Google Scholar 

  3. C. T. Cole, Jr., K. L. Chien andC. H. Propster Jr., “A transistorized trascribing card punch”, Proc. Eastern Joint Comp. Conf., (1956), 80–83.

  4. D. Gipp, R. D. Lohman, R. R. Painter andB. Zuk, “Highspeed logic using low-cost mesa transistors”, Semicond. Prod.,4, (1961), 31–35.

    Google Scholar 

Strutture NAND o NOR tipo DCTL

  1. J. W. Easley, “Transistor characteristics for direct coupled transistor logic circuits”, IRE Trans. on El. Comp.,EC-7, (1958), 6–16.

    Google Scholar 

  2. J. R. Riggs, “Digital logic modules”, Electro-Tech.,68, (1961), 64–72.

    Google Scholar 

Circuiti NAND o NOR a diodi tunnell

  1. G. W. Neff, S. A. Butler, D. L. Critchlow, “Esaki (tunnel) diode logic circuits”, Digest of Tech. Pap. Solid State Circ. Conf., 1960, 16–17.

  2. M. H. Lewin, A. G. Samusenks, A. W. Lo, “The tunnel diode as a logic element”, Digest of Tech. Papers, Solid State Circuits Conf., 1960, 10–11.

  3. E. Goto, et al., “Esaki diode high-speed logical circuits”, IRE Trans. on El. Comp.,EC-9, (1960), 25–29.

    Google Scholar 

  4. H. S. Yourke, S. A. Butler, W. G. Strohm, “Esaki diode NOT-OR logic circuits”, IRE Trans. on El. Comp.,EC-10, (1961), 183–190.

    Article  Google Scholar 

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  1. Istituto Elettrotecnico Nazionale Galileo Ferraris, Torino

    A. R. Meo

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Meo, A.R. Sulla sintesi di reti NAND o nor a molti livelli. Calcolo 3, 1–82 (1966). https://doi.org/10.1007/BF02576743

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