Abstract
A chip set for pipelined and parallel pipelined FFT applications is presented. The set consists of two cascadeable chips with built-in self-test and a chip-interconnectivity test feature. The two ASICs are a 15k gate Complex-Butterfly and a 9k gate FFT Switch. The Complex-Butterfly uses redundant binary arithmetic (RBA), a modified Booth algorithm and a Wallace tree architecture to achieve a throughput of better than 25 Msamples/sec. The cascadeable FFT Switch is designed to support the implementation of radix-2, 2N point, pipeline FFTs. Both devices have been fabricated in 1.5μm CMOS gate array technology.
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Szwarc, V., Desormeaux, L., Wong, W. et al. A chip set for pipeline and parallel pipeline FFT architectures. Journal of VLSI Signal Processing 8, 253–265 (1994). https://doi.org/10.1007/BF02106450
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DOI: https://doi.org/10.1007/BF02106450