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Bridging defects resistance in the metal layer of a CMOS process

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Abstract

The resistance value of bridging defects in CMOS VLSI circuits are evaluated through a set of measurements performed on process-related defect monitoring wafers. The monitor circuits considered are made of metal1 lines. The results show how the vast majority of the measured metal1 to metal1 bridges has a low resistance. Only a small percentage of the overall bridges resulted in a resistance value above 500 Ω, while the exact percentage can vary from batch to batch. This high resistance does not seem to be the result of the material of the defect itself, since all these bridging defects were found to be caused by extra aluminium. The shape and location of the defect seem to be the cause of the high resistance values probably caused by poor contacts between the extra metal and the designed monitor lines.

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Authors and Affiliations

  1. Depart. d'Enginyeria Electrònica, Universitat Politècnica de Catalunya, Diagonal 647, 08028, Barcelona, Spain

    R. Rodríguez-Montañés

  2. Philips Research Laboratories, P.O. Box 80000, 5600 JA, Eindhoven, The Netherlands

    E. M. J. G. Bruls

  3. Universitat Politècnica de Catalunya, Depart. d'Enginyeria Electrònica, Diagonal 647, 08028, Barcelona, Spain

    J. Figueras

Authors
  1. R. Rodríguez-Montañés
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  2. E. M. J. G. Bruls
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  3. J. Figueras
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Additional information

This work has been partially supported by the Project ARCHIMEDES (ESPRIT III BRA Program Project No 7107) and by the Comisión Interministerial para la Ciencia y Tecnología (C.I.C.Y.T.), Project No. TIC 94-0561.

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Rodríguez-Montañés, R., Bruls, E.M.J.G. & Figueras, J. Bridging defects resistance in the metal layer of a CMOS process. J Electron Test 8, 35–46 (1996). https://doi.org/10.1007/BF00136074

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  • DOI: https://doi.org/10.1007/BF00136074

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