Design of a Fault-Tolerant Conditional Sum Adder

Abstract

Fault tolerance is the ability of a system to retain its normal operation without failure when some part of the system fails to operate properly. It increases the wear-out time for any system at a cost of increased hardware. Fault tolerant approaches must be incorporated in any safety-critical system for continuing its job without failure even if an error occurs in the system. Adder is the most essential block in any digital architecture. In this Paper we present the design of a fault tolerant conditional sum adder with an efficient testing methodology and self-reconfiguring approach.