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Design of Fault Tolerant Adders: A Review

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Abstract

Arithmetic circuits, especially the adder, are the heart of any computing system that comprises numerous processing units ranging from small digital systems to supercomputers. As a result of the shrinking size of electronic devices, the rate of occurrence of soft errors has increased. Thus, designing soft error tolerant circuits is of great importance. In this paper, various fault tolerant designs required to attain highly reliable adders are depicted. In addition to the review of different fault tolerant designs of carry look-ahead and carry-select adders, this paper also gives their comparative assessment in terms of fault tolerance, area overhead, and weaknesses. The described fault tolerant designs are classified based on their ability to detect or correct faults and the employed redundancy scheme.

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Authors and Affiliations

  1. College of Computer Sciences and Engineering, King Fahd University of Petroleum & Minerals, Dhahran, 31261, Saudi Arabia

    Ghashmi H. Bin Talib, Aiman H. El-Maleh & Sadiq M. Sait

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  1. Ghashmi H. Bin Talib
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Bin Talib, G.H., El-Maleh, A.H. & Sait, S.M. Design of Fault Tolerant Adders: A Review. Arab J Sci Eng 43, 6667–6692 (2018). https://doi.org/10.1007/s13369-018-3556-9

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