Abstract
Networks–on–Chip (NoCs) have been proposed as a promising solution to the complex on-chip communication problems derived from the increasing number of processor cores. The design of NoCs involves several key issues, being the topological mapping (the mapping of the Intellectual Properties (IPs) to network nodes) one of them. Several proposals have been focused on topological mapping last years, but they require the experimental validation of each mapping considered.
In this paper, we propose a communication-aware topological mapping technique for NoCs. This technique is based on the experimental correlation of the network model with the actual network performance, thus avoiding the need to experimentally evaluate each mapping explored. The evaluation results show that the proposed technique can provide better performance than the currently existing techniques (in terms of both network latency and energy consumption). Additionally, it can be used for both regular and irregular topologies.
This work has been jointly supported by the Spanish MEC, the European Commission FEDER funds, the HiPEAC network of excellence, and the University of Valencia under grants Consolider-Ingenio 2010 CSD2006-00046, TIN2006-15516-C04-04, HiPEAC cluster 1169, and UV-BVSPIE-07-1884.
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Keywords
- Network Node
- Mapping Technique
- Average Latency
- Greedy Randomize Adaptive Search Procedure
- Topological Mapping
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Tornero, R., Orduña, J.M., Palesi, M., Duato, J. (2008). A Communication-Aware Topological Mapping Technique for NoCs. In: Luque, E., Margalef, T., Benítez, D. (eds) Euro-Par 2008 – Parallel Processing. Euro-Par 2008. Lecture Notes in Computer Science, vol 5168. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85451-7_98
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DOI: https://doi.org/10.1007/978-3-540-85451-7_98
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