Abstract
In this paper we present a networked lightweight and partially reconfigurable platform assisted by a remote bitstreams server. We propose a software and hardware architecture as well as a new data-link level network protocol implementation dedicated to dynamic and partial reconfiguration of FPGAs. It requires a network controller and much less external memories to store reconfiguration software, bitstreams and buffer pools used by standard communication protocols. Our measures, based on a real implementation, show that our system can download remote bistreams with a reconfiguration speed ten times faster than known solutions.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Hubner, M., Ullmann, M., Weissel, F., Becker, J.: Real-time Configuration Code Decompression for Dynamic FPGA Self-Reconfiguration. In: Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004) (2004)
Blodget, B., McMillan, S., Lysaght, P.: A lightweight approach for embedded reconfiguration of fpgas. In: Proceedings of Design, Automation and Test in Europe (DATE 2003) (2003)
Claus, C., Zeppenfeld, J., Muller, F., Stechele, W.: Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System. DATE 2007
Web Server design using MicroBlaze Soft Processor, Xilinx, XAPP433 (October 2006)
Dunkels, A.: lwIP, Computer and Networks Architectures (CNA), Swedish Institute of Computer Science, http://www.sics.se/~adam/lwip/
Lagger, A., Upegui, A., Sanchez, E.: Self-Reconfigurable Pervasive Platform For Cryptographic Application. In: Proceedings of International Conference on Field Programmable Logic and Applications (FPL 2006) (2006)
Williams, J., Bergmann, N.: Embedded Linux as a platform for dynamically self-reconfiguring systems-on-chip. In: Proceedings of the 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2004) (2004) ISBN 1-932415-42-4
Huebner, M., Becker, T., Becker, J.: Real-Time LUT-based Network Topologies for Dynamic and Partial FPGA Self-Reconfiguration. In: 17th Symposium on Integrated Circuits and Systems Design (SBCCI 2004) (September 2004)
Bobda, C., Majer, M., Ahmadinia, A., Haller, T., Linarth, A., Teich, J.: The Erlangen Slot Machine: Increasing Flexibility in FPGA-Based Reconfigurable Platforms. Journal of VLSI Signal Processing Systems 47(1), 15–31 (2007)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Bomel, P., Gogniat, G., Diguet, JP. (2008). A Networked, Lightweight and Partially Reconfigurable Platform. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_35
Download citation
DOI: https://doi.org/10.1007/978-3-540-78610-8_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78609-2
Online ISBN: 978-3-540-78610-8
eBook Packages: Computer ScienceComputer Science (R0)