Abstract
In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications. Key features of PARO are: (1) The design entry in form of a compact and intuitive functional programming language which allows highly parallel implementations. (2) Advanced partitioning techniques are applied in order to balance the trade-offs in cost and performance along with requisite throughputs. This is obtained by distributing computations onto an array of tightly coupled processor elements. (3) We demonstrate the performance of the FPGA synthesized hardware with several selected algorithms from different benchmarks.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Dutta, H., Hannig, F., Ruckdeschel, H., Teich, J.: Efficient Control Generation for Mapping Nested Loop Programs onto Processor Arrays. Journal of Systems Architecture 53(5–6), 300–309 (2007)
Dutta, H., Hannig, F., Teich, J.: Hierarchical Partitioning for Piecewise Linear Algorithms. In: Proceedings of the 5th International Conference on Parallel Computing in Electrical Engineering (PARELEC), Bialystok, Poland, September 2006, pp. 153–160 (2006)
Dutta, H., Hannig, F., Teich, J., Heigl, B., Hornegger, H.: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. In: Proceedings of IEEE 17th International Conference on Application-specific Systems, Architectures, and Processors (ASAP), Steamboat Springs, CO, USA, pp. 331–337 (September 2006)
Forte Design Systems, http://www.forteds.com
Guillou, A., Quinton, P., Risset, T.: Hardware Synthesis for Multi-Dimensional Time. In: Proceedings of IEEE 14th International Conference on Application-specific Systems, Architectures, and Processors (ASAP), pp. 40–50, The Hague, The Netherlands (June 2003)
Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: SPARK: A High-Level Synthesis Framework for Applying Parallelizing Compiler Transformations. In: Proceedings of the 16th International Conference on VLSI Design, pp. 461–466 (January 2003)
Hannig, F., Teich, J.: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. In: Proceedings of the 15th IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), Galveston, TX, USA, pp. 17–27 (September 2004)
Lee, C., Potkonjak, M., Mangione-Smith, W.H.: MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. In: International Symposium on Microarchitecture, pp. 330–335 (1997)
Mentor Graphics Corp, http://www.mentor.com
Ruckdeschel, H., Dutta, H., Hannig, F., Teich, J.: Automatic FIR Filter Generation for FPGAs. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds.) SAMOS 2005. LNCS, vol. 3553, pp. 51–61. Springer, Heidelberg (2005)
Synfora, Inc., http://www.synfora.com
Teich, J., Thiele, L., Zhang, L.: Scheduling of Partitioned Regular Algorithms on Processor Arrays with Constrained Resources. J. of VLSI Signal Processing 17(1), 5–20 (1997)
Thompson, S.: Haskell: The Craft of Functional Programming. Addison Wesley, Reading (1999)
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 2008 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Hannig, F., Ruckdeschel, H., Dutta, H., Teich, J. (2008). PARO: Synthesis of Hardware Accelerators for Multi-dimensional Dataflow-Intensive Applications. In: Woods, R., Compton, K., Bouganis, C., Diniz, P.C. (eds) Reconfigurable Computing: Architectures, Tools and Applications. ARC 2008. Lecture Notes in Computer Science, vol 4943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-78610-8_30
Download citation
DOI: https://doi.org/10.1007/978-3-540-78610-8_30
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-78609-2
Online ISBN: 978-3-540-78610-8
eBook Packages: Computer ScienceComputer Science (R0)