Abstract
Hierarchical convolutional neural networks are a well-known robust image-recognition model. In order to apply this model to robot vision or various intelligent real-time vision systems, its VLSI implementation is essential. This paper proposes a new algorithm for reducing multiply-and-accumulation operation by thresholding in a projection field and by performing weight decomposition in a 2-D neuron array. We also propose a VLSI architecture based on the proposed algorithm, and estimate its operation performance.
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References
Fukushima, K., Miyake, S.: Neocognitron: A new algorithm for pattern recognition tolerant of deformations and shifts in position. Pattern Recognition 15, 455–469 (1982)
Lawrence, S., Giles, C.L., Tsoi, A.C., Back, A.D.: Face recognition: A convolutional neural-network approach. IEEE Trans. Neural Networks 8, 98–113 (1997)
Neubauer, C.: Evaluation of convolutional neural networks for visual recognition. IEEE Trans. Neural Networks 9, 685–696 (1998)
Matsugu, M.: Hierarchical pulse-coupled neural network model with temporal coding and emergent feature binding mechanism. In: Proc. Int. Joint Conf. on Neural Networks (IJCNN), pp. 802–807 (2001)
Matsugu, M., Mori, K., Ishii, M., Mitarai, Y.: Convolutional spiking neural network model for robust face detection. In: Proc. Int. Conf. on Neural Information Processing (ICONIP), pp. 660–664 (2002)
Boser, B.E., Säckinger, E., Bromley, J., Cun, Y.L., Jackel, L.D.: An analog neural network processor with programmable topology. IEEE J. Solid-State Circuits 26, 2017–2025 (1991)
Korekado, K., Morie, T., Nomura, O., Ando, H., Nakano, T., Matsugu, M., Iwata, A.: A convolutional neural network VLSI for image recognition using merged/mixed analog-digital architecture. In: Palade, V., Howlett, R.J., Jain, L. (eds.) KES 2003. LNCS, vol. 2773, pp. 169–176. Springer, Heidelberg (2003)
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Nomura, O., Morie, T., Korekado, K., Matsugu, M., Iwata, A. (2004). A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. In: Negoita, M.G., Howlett, R.J., Jain, L.C. (eds) Knowledge-Based Intelligent Information and Engineering Systems. KES 2004. Lecture Notes in Computer Science(), vol 3213. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-30132-5_134
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DOI: https://doi.org/10.1007/978-3-540-30132-5_134
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-23318-3
Online ISBN: 978-3-540-30132-5
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