Overview
- Presents successive RISC-V processor implementations in increasing difficulty
- Codes can serve as labs for a computer processor architecture course
- Concisely introduces the RISC-V open-source machine language
Part of the book series: Undergraduate Topics in Computer Science (UTICS)
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Table of contents (14 chapters)
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Front Matter
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Single Core Processors
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Front Matter
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Back Matter
Keywords
About this book
Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors).
The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development.
Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators.
Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.
Authors and Affiliations
About the author
Bibliographic Information
Book Title: Guide to Computer Processor Architecture
Book Subtitle: A RISC-V Approach, with High-Level Synthesis
Authors: Bernard Goossens
Series Title: Undergraduate Topics in Computer Science
DOI: https://doi.org/10.1007/978-3-031-18023-1
Publisher: Springer Cham
eBook Packages: Computer Science, Computer Science (R0)
Copyright Information: The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023
Softcover ISBN: 978-3-031-18022-4Published: 26 January 2023
eBook ISBN: 978-3-031-18023-1Published: 25 January 2023
Series ISSN: 1863-7310
Series E-ISSN: 2197-1781
Edition Number: 1
Number of Pages: XXV, 439
Number of Illustrations: 65 b/w illustrations, 196 illustrations in colour
Topics: Processor Architectures, Computer Hardware, Control Structures and Microprogramming, Operating Systems, Software Engineering/Programming and Operating Systems