A Multicore RISC-V Processor with Multihart Cores

Abstract

This chapter will make you build your second multicore RISC-V CPU. The processor is built from multiple IPs, each being a copy of the multihart_ip presented in Chap. 10. Each core runs multiple harts. Each core has its own code and data memories. The code memory is common to all the harts of the core. The data memory of the core is partitioned between the implemented harts. Hence, a c core with h hart processor has h*c data memory partitions embedded in c memory IPs. The data memory banks are interconnected with an AXI interconnect IP. Any hart has a private access to its data memory partition and any other partition of the same core, and a remote access to any partition of any other core. An example of a parallelized matrix multiplication is used to measure the speedup when moving the number of cores from one to four and the number of harts from one to eight with a maximum of 16 harts in the whole IPs for simulation and a maximum of eight implementable harts on the FPGA.