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Formal Hardware Verification Methods: A Survey

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Computer-Aided Verification

Abstract

Growing advances in VLSI technology have led to an increased level of complexity in current hardware systems. Late detection of design errors typically results in higher costs due to the associated time delay as well as loss of production. Thus it is important that hardware designs be free of errors. Formal verification has become an increasingly important technique towards establishing the correctness of hardware designs. In this article we survey the research that has been done in this area, with an emphasis on more recent trends. We present a classification framework for the various methods, based on the forms of the specification, the implementation, and the proof method. This framework enables us to better highlight the relationships and interactions between seemingly different approaches.

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  1. School of Computer Science, Carnegie Mellon University, 5000 Forbes Ave., Pittsburgh, Pennsylvania, 15213, USA

    Aarti Gupta

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  1. AT&T Bell Laboratories, USA

    Robert Kurshan

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Gupta, A. (1992). Formal Hardware Verification Methods: A Survey. In: Kurshan, R. (eds) Computer-Aided Verification. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3556-0_2

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