Abstract
We present a methodology in which the behavior of a switch level device is specified using abstract parameterized regular expressions. These specifications are used to generate a finite automaton representing an abstraction of the behavior of a block of memory comprised of a set of such switch level devices. The automaton, in conjunction with an Efficient Memory Model [1], [2] for the devices, forms a symbolic simulation model representing an abstraction of the array core embedded in a larger design under analysis. Using Symbolic Trajectory Evaluation, we check the equivalence between a register transfer level description and a schematic description augmented with abstract specifications for one of the custom memories embedded in the MPC7450 PowerPC processor.
PowerPC is a trademark of the International Business Machines Corporation, used under license therefrom.
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© 2001 Springer-Verlag Berlin Heidelberg
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Bhadra, J., Martin, A., Abraham, J., Abadir, M. (2001). Using Abstract Specifications to Verify PowerPC™ Custom Memories by Symbolic Trajectory Evaluation. In: Margaria, T., Melham, T. (eds) Correct Hardware Design and Verification Methods. CHARME 2001. Lecture Notes in Computer Science, vol 2144. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44798-9_30
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DOI: https://doi.org/10.1007/3-540-44798-9_30
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