Abstract
An investigation was conducted on the characteristics of current and voltage in a heterostructure setup comprising a CdS/Silicon Schottky barrier diode. The investigation encompassed a broad spectrum of temperature conditions, spanning from 200 to 400 K. Based on the simulation results, the saturation current, ideality factor, series resistance measurement, and Schottky barrier height demonstrated favorable outcomes. Based on this premise, empirical evidence demonstrates that an increase in temperatures leads to a decrease in the ideality factor, accompanied by an increase in the barrier height. The temperature alterations within the implemented heterostructure lead to a Schottky barrier height ranging from 1.2 to 1.5 eV. At temperatures below 300 K, the height of the barrier exhibited slight irregularity, which became more pronounced with increasing temperature. Furthermore, an analysis was conducted on the C–V and G–V characteristics of the CdS/Si heterostructure. Various analyses of C–V and G–V have been conducted in order to gain a comprehensive understanding of the structure. A C–V analysis was conducted for frequencies of 1 kHz and 1 MHz, while also considering temperature variations. The G–V experiment encompassed a frequency range of 1 KHz to 1 MHz, as well as variations in temperature. Throughout the investigation, various factors such as effective barrier height and built-in voltage were identified. Based on the results obtained from the investigation, it has been determined that the effective barrier height at room temperature is 0.98 eV.
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Rajendran, J., Raju, L. & Bojaraj, L. Analytical assessment of Schottky diodes based on CdS/Si heterostructure: current, capacitance, and conductance analysis using TCAD. Indian J Phys (2024). https://doi.org/10.1007/s12648-023-03052-9
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DOI: https://doi.org/10.1007/s12648-023-03052-9