Abstract
In recent years, Cu–Sn solid–liquid interdiffusion (SLID) bonding has been used in semiconductor packaging, die-attach, fine-pitch interconnection, and through-silicon vias (TSV)-based 3D stacking applications. Due to its specific advantages such as lower cost, less stringent surface uniformity requirements, higher thermal bond stability, and relatively lower processing temperatures, electrodeposited Cu–Sn-based bonding is explored to achieve wafer-level hermetic encapsulation of miniaturized sensors; however, the overall reliability of Cu–Sn bonds remains a challenge. The voids formed in the electrodeposited Cu–Sn layers and the brittle nature of the formed intermetallic compounds (IMC) affects the long term reliability of the Cu–Sn SLID bonds. A significant concern is the sporadic interfacial void formation within the Cu–Sn layers during the bonding process and high-temperature applications. This review article summarizes the different mechanisms of the IMC formation and their growth and explores the reasons behind the interfacial voids formed in the electrodeposited Cu–Sn layers when these are annealed at different temperatures ranging from 150 to 300 °C. A detailed description of the IMC and void formation and their subsequent growth in the thick electrodeposited Cu–Sn layers is presented, along with the various design parameters affecting the IMC growth during the bonding process. Various remedies to minimize these interfacial voids are also suggested. Higher bonding pressure, lower processing temperature, and reduced surface roughness are the key factors affecting the void size and voids density. The chemical impurity in the copper electrolyte and the resultant surface roughness affect the interfacial void formation in the electrodeposited Cu–Sn layers. This review will help minimize the interfacial voids and, thus, obtain higher bond reliability.
Similar content being viewed by others
References
C. B. O’Neal, A. P. Malshe, S. B. Singh, W. D. Brown, and W. P. Eaton, “Challenges in the packaging of MEMS,” Proc. - Int. Symp. Adv. Packag. Mater. Process. Prop. Interfaces, (1999) 41–47. Doi:https://doi.org/10.1109/ISAPM.1999.757284
M. Esashi, Wafer level packaging of MEMS. J. Micromechanics Microengineering 18, 73001–730012 (2008). https://doi.org/10.1088/0960-1317/18/7/073001
N. Belkadi, K. Nadaud, C. Hallepee, D. Passerieux, P. Blondy, Zero-Level Packaged RF-MEMS Switched Capacitors on Glass Substrates. J. Microelectromechanical Syst. 29, 109–116 (2020). https://doi.org/10.1109/JMEMS.2019.2949949
B. Luo, M. Ma, M.A. Zhang, J. Shang, C.P. Wong, “Composite Glass-Silicon Substrates Embedded with Microcomponents for MEMS System Integration”, IEEE Trans. Components. Packag. Manuf. Technol. 9, 201–208 (2019). https://doi.org/10.1109/TCPMT.2018.2889368
O. Temel, Y.E. Kalay, T. Akin, Wafer-Level Low-Temperature Solid-Liquid Inter-Diffusion Bonding With Thin Au-Sn Layers for MEMS Encapsulation. J. Microelectromechanical Syst. 30, 64–71 (2020). https://doi.org/10.1109/JMEMS.2020.3040039
W. Zhang, J. Gu, L. Li, X. Li, Through-Glass-Via Based Microstrip Band-Pass Filters Fabricated with Wafer-Level Low-Melting-Point Alloy Micro-Casting. IEEE Electron Device Lett. 41, 1106–1109 (2020). https://doi.org/10.1109/LED.2020.2993615
K. Zoschke et al., “Cap Fabrication and Transfer Bonding Technology for Hermetic and Quasi Hermetic Wafer Level MEMS Packaging,” in Electronic Components and Technology Conference (2020) 432–438. Doi:https://doi.org/10.1109/ECTC32862.2020.00076
H.K. Kannojia, J. Arab, B.J. Pegu, P. Dixit, Fabrication and Characterization of Through-Glass Vias by the ECDM Process. J. Electrochem. Soc. 166, D531–D538 (2019). https://doi.org/10.1149/2.0141913jes
A. Duan, T.T. Luu, K. Wang, K. Aasmundtveit, N. Hoivik, Wafer-level Cu-Sn micro-joints with high mechanical strength and low Sn overflow. J. Micromechanics Microengineering. 25, 97001 (2015). https://doi.org/10.1088/0960-1317/25/9/097001
R.R. Tummala, Fundamentals of Microsystems Packaging. Soldering & Surface Mount Technology (2003). https://doi.org/10.1108/ssmt.2003.21915aae.006
S. Farrens, Metal based wafer level packaging, Proc. Int. Wafer- Lev. Packag. Conf. (2008) 8–14.
C. Ko, K. Chen, Low temperature bonding technology for 3D integration. Microelectron. Reliab. 52, 302–311 (2012). https://doi.org/10.1016/j.microrel.2011.03.038
Y.I. Kim, K.H. Yang, W.S. Lee, 2004 Thermal degradation of DRAM retention time: Characterization and improving techniques, in:IEEE Int. Reliab. Phys. Symp. Proc., 667–668. Doi:https://doi.org/10.1109/RELPHY.2004.1315442.
C. Ko, K. Chen, Wafer-level bonding/stacking technology for 3D integration. Microelectron. Reliab. 50, 481–488 (2010). https://doi.org/10.1016/j.microrel.2009.09.015
H. Liu, K. Wang, K.E. Aasmundtveit, N. Hoivik, Intermetallic Compound Formation Mechanisms for Cu-Sn Solid-Liquid Interdiffusion Bonding. J. Electron. Mater. 41, 2453–2462 (2012). https://doi.org/10.1007/s11664-012-2060-3
B.S. Lee, S.K. Hyun, J.W. Yoon, Cu–Sn and Ni–Sn transient liquid phase bonding for die-attach technology applications in high-temperature power electronics packaging. J. Mater. Sci. Mater. Electron. 28, 7827–7833 (2017). https://doi.org/10.1007/s10854-017-6479-4
C. Yuhan, L. Le, Wafer Level hermetic packaging based on Cu-Sn isothermal solidification technology. J. Semicond. 30, 4–8 (2009). https://doi.org/10.1088/1674-4926/30/8/086001
B. Balakrisnan, C.C. Chum, M. Li, Z. Chen, T. Cahyadi, Fracture Toughness of Cu-Sn Intermetallic Thin Films. J. Electron. Mater. 32, 166–171 (2003). https://doi.org/10.1007/s11664-003-0188-x
B.H. Kwak, M.H. Jeong, J.W. Kim, B. Lee, H.J. Lee, Y.B. Park, Correlations between interfacial reactions and bonding strengths of Cu/Sn/Cu pillar bump. Microelectron. Eng. 89, 65–69 (2012). https://doi.org/10.1016/j.mee.2011.01.020
A. Paul, Growth mechanism of phases, Kirkendall voids, marker plane position and indication of the relative mobilities of the species in the interdiffusion zone. J. Mater. Sci. Mater. Electron. 22, 833–837 (2011). https://doi.org/10.1007/s10854-010-0220-x
K. Zeng, R. Stierman, T. Chiu, D. Edwards, K. Ano, K.N. Tu, Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability. J. Appl. Phys. 97, 1–8 (2005). https://doi.org/10.1063/1.1839637
G. Ross, V. Vuorinen, M. Paulasto-Kröckel, Void formation and its impact on Cu-Sn intermetallic compound formation. J. Alloys Compd. 677, 127–138 (2016). https://doi.org/10.1016/j.jallcom.2016.03.193
G. Ross, P. Malmberg, V. Vuorinen, M. Paulasto-Kröckel, The Role of Ultrafine Crystalline Behavior and Trace Impurities in Copper on Intermetallic Void Formation. ACS Appl. Electron. Mater. 1, 88–95 (2019). https://doi.org/10.1021/acsaelm.8b00029
H.K. Kannojia, P. Dixit, Effect of surface roughness on void formation and intermetallic growth in electrodeposited Cu-Sn stacks. Mater. Lett. 257, 126710 (2019). https://doi.org/10.1016/j.matlet.2019.126710
H. Xu, T. Suni, V. Vuorinen, J. Li, H. Heikkinen, P. Monnoyer, M. Paulasto-Kröckel, Wafer-level SLID bonding for MEMS encapsulation. Adv. Manuf. 1, 226–235 (2013). https://doi.org/10.1007/s40436-013-0035-0
T.A. Tollefsen, A. Larsson, O.M. Løvvik, K. Aasmundtveit, Au-Sn SLID Bonding - Properties and Possibilities. Metall. Mater. Trans. B. 43, 397–405 (2012). https://doi.org/10.1007/s11663-011-9609-z
A. Munding, H. Hubner, A. Kaiser, S. Penka, P. Benkart, E. Kohn, Wafer Level 3-D ICs Process Technology, Springer. New York (2008). https://doi.org/10.1007/978-0-387-76534-1
C.C. Lee, C.Y. Wang, G. Matijasevic, Advances in Bonding Technology for Electronic Packaging. J. Electron. Packag. 115, 201–207 (1993). https://doi.org/10.1115/1.2909318
G.S. Matijasevic, C.C. Lee, C.Y. Wang, Au-Sn alloy phase diagram and properties related to its use as a bonding medium. Thin Solid Films 223, 276–287 (1993). https://doi.org/10.1016/0040-6090(93)90533-U
R.W. Johnson, C. Wang, Y. Liu, J.D. Scofield, Power Device Packaging Technologies for Extreme Environments. IEEE Trans. Electron. Packag. Manuf. 30, 182–193 (2007). https://doi.org/10.1109/TEPM.2007.899158
K. Wang, K. Aasmundtveit, H. Jakobsen, Surface Evolution and Bonding Properties of Electroplated Au/Sn/Au, in: 2nd Electron. Syst. Integr. Technol. Conf., IEEE, Greenwich, 2008: pp. 1131–1134. Doi:https://doi.org/10.1109/ESTC.2008.4684511.
T.T. Luu, N. Hoivik, K. Wang, K.E. Aasmundtveit, A.B. Vardøy, Characterization of Wafer-Level Au-In-Bonded Samples at Elevated Temperatures. Metall. Mater. Trans. A. 46, 2637–2645 (2015). https://doi.org/10.1007/s11661-015-2865-9
N. Hoivik, K. Wang, K. Aasmundtveit, G. Salomonsen, A. Lapadatu, G. Kittilsland, B. Stark, Fluxless Wafer-Level Cu-Sn Bonding for Micro- and Nanosystems Packaging, in: Electron. Syst. Technol. Conf., IEEE, Berlin, 2010: pp. 1–5. Doi:https://doi.org/10.1109/ESTC.2010.5643013.
A. Lapadatu, T.I. Simonsen, G. Kittilsland, B. Stark, N. Hoivik, V. Dalsrud, G. Salomonsen, Cu-Sn Wafer Level Bonding for Vacuum Encapsulation of Microbolometers Focal Plane Arrays. Electrochem. Soc. 33, 73–82 (2010). https://doi.org/10.1149/1.3483495
H. Liu, G. Salomonsen, K. Wang, K.E. Aasmundtveit, N. Hoivik, Wafer-Level Cu/Sn to Cu/Sn SLID-Bonded Interconnects with Increased Strength, IEEE Trans. Components. Packag. Manuf. Technol. 1, 1350–1358 (2011). https://doi.org/10.1109/TCPMT.2011.2156793
T.T. Luu, A.N.I. Duan, K.E. Aasmundtveit, N. Hoivik, Optimized Cu-Sn Wafer-Level Bonding Using Intermetallic Phase Characterization. J. Electron. Mater. 42, 3582–3592 (2013). https://doi.org/10.1007/s11664-013-2711-z
M.H. Jeong, J.W. Kim, B.H. Kwak, Y.B. Park, Effects of annealing and current stressing on the intermetallic compounds growth kinetics of Cu/thin Sn/Cu bump. Microelectron. Eng. 89, 50–54 (2012). https://doi.org/10.1016/j.mee.2011.04.025
T.T. Luu, N. Hoivik, K. Wang, K.E. Aasmundtveit, A.B. Vardøy, High-Temperature Mechanical Integrity of Cu-Sn SLID Wafer-Level Bonds. Metall. Mater. Trans. A. 46, 5266–5274 (2015). https://doi.org/10.1007/s11661-015-3068-0
N. Hoivik, K. Aasmundtveit, Wafer-Level Solid-Liquid Interdiffusion Bonding, in Handbook of Wafer Bonding. ed. by N. Hoivik (Wiley, New Jersey, 2012)
V. Vuorinen, H. Dong, G. Ross, J. Hotchkiss, J. Kaaos, M. Paulasto-Kröckel, Wafer Level Solid Liquid Interdiffusion Bonding: Formation and Evolution of Microstructures. J. Electron. Mater. 1, 1–7 (2020). https://doi.org/10.1007/s11664-020-08530-y
K.E. Aasmundtveit, T. Eggen, T. Manh, H.V. Nguyen, In–Bi low-temperature SLID bonding for piezoelectric materials. Solder. Surf. Mt. Technol. 30, 100–105 (2018). https://doi.org/10.1108/SSMT-10-2017-0034
W.J. Reichenecker, Electrical Conductivity of the Copper-Tin Intermetallic Compound. Weld. J. 59, 308–310 (1980)
H.P.R. Frederikse, R.J. Fields, A. Feldman, Thermal and electrical properties of copper-tin and nickel-tin intermetallics. J. Appl. Phys. 72, 2879–2882 (1992). https://doi.org/10.1063/1.351487
B.J. Grummel, H.A. Mustain, Z.J. Shen, J.C. Elmes, A.R. Hefner, “Reliability characterization of Au-In transient liquid phase bonding through electrical resistivity measurement”, IEEE Trans. Components. Packag. Manuf. Technol. 5, 1726–1733 (2015). https://doi.org/10.1109/TCPMT.2015.2489686
D. Frear, S. Burchett, A.H. Morgan, J.H. Lau, Mechanics of Solder Alloy Interconnects (Springer Science and Business Media, Germany, 1994).
A. Zayed, M. Saliqur, P.Y. Chia, A.S.M.A. Haseeb, Mechanical properties of intermetallic compounds in electrodeposited multilayered thin fi lm at small scale by nanoindentation. Mater. Lett. 147, 50–53 (2015). https://doi.org/10.1016/j.matlet.2015.01.127
G. Ross, Intermetallic Void Formation in Cu-Sn Micro-Connects (Aalto University, Finland, 2019).
T. Laurila, V. Vuorinen, J.K. Kivilahti, Interfacial reactions between lead-free solders and common base materials. Mater. Sci. Eng. R Reports. 49, 1–60 (2005). https://doi.org/10.1016/j.mser.2005.03.001
H. Xu, A. Rautiainen, V. Vuorinen, E. Österlund, T. Suni, H. Heikkinen, P. Monnoyer, Reliability Performance of Au-Sn and Cu-Sn Wafer Level SLID Bonds for MEMS. Electron. Syst. Conf. 1–5 (2014). https://doi.org/10.1109/ESTC.2014.6962771
S. Fürtauer, D. Li, D. Cupid, H. Flandorfer, The Cu–Sn phase diagram, Part I: New experimental results. Intermetallics 34, 142–147 (2013). https://doi.org/10.1016/j.intermet.2012.10.004
K.N. Tu, Interdiffusion and reaction in bimetallic Cu-Sn films. Acta Mater. 21, 347–354 (1973). https://doi.org/10.1016/0001-6160(73)90190-9
J.D. Mcbrayer, R.M. Swanson, T.W. Sigmon, Diffusion of Metals in Silicon Dioxide. J. Electrochem. Soc. 133, 1242–1246 (1986). https://doi.org/10.1149/1.2108827
K.N. Tu, R.D. Thompson, Kinetics of interfacial reaction in bimetallic CuSn thin films. Acta Metall. 30, 947–952 (1982). https://doi.org/10.1016/0001-6160(82)90201-2
T.N. Rhodin, Low Temperature Oxidation of Copper. I. Physical Mechanism, J. Am. Chem. Soc. 72 (1950) 5102–5106. https://doi.org/https://doi.org/10.1021/ja01167a079.
H.K. Kannojia, S.K. Sharma, P. Dixit, Void Formation and Intermetallic Growth in Pulse Electrodeposited Cu-Sn Layers for MEMS Packaging. J. Electron. Mater. 47, 7386–7400 (2018). https://doi.org/10.1007/s11664-018-6679-6
K.N. Tu, Cu/Sn interfacial reactions: thin-film case versus bulk case. Mater. Chem. Phys. 46, 217–223 (1996). https://doi.org/10.1016/S0254-0584(97)80016-8
H.K. Kim, K.N. Tu, Kinetic Analysis of the Soldering Reaction between Eutectic SnPb alloy and Cu accompanied by Ripening. Phys. Rev. B. 53, 27–34 (1996). https://doi.org/10.1103/PhysRevB.53.16027
J.S. Kang, R.A. Gagliano, G. Ghosh, M.E. Fine, Isothermal Solidification of Cu/Sn Diffusion Couples to Form Thin-Solder Joints. J. Electron. Mater. 31, 1238–1243 (2002). https://doi.org/10.1007/s11664-002-0015-9
S. Bader, W. Gust, H. Hieber, Rapid Formation of Intermetallics Compounds by Interdiffusion in the Cu-Sn and Ni-Sn Sysytems. Acta Metall. Mater. 43, 329–337 (1995). https://doi.org/10.1016/0956-7151(95)90289-9
H.T. Ma, L. Qu, M.L. Huang, L.Y. Gu, N. Zhao, L. Wang, In-situ study on growth behavior of Ag3Sn in Sn-3.5Ag/Cu soldering reaction by synchrotron radiation real-time imaging technology. J. Alloys Compd. 537, 286–290 (2012). https://doi.org/10.1016/j.jallcom.2012.05.055
L. Qu, N. Zhao, H.J. Zhao, M.L. Huang, H.T. Ma, In situ study of the real-time growth behavior of Cu6Sn 5 at the Sn/Cu interface during the soldering reaction. Scr. Mater. 72–73, 43–46 (2014). https://doi.org/10.1016/j.scriptamat.2013.10.013
M. Oh, (1994) Growth Kinetics of Intermetallic Phases in the Cu-Sn Binary and the Cu-Ni-Sn Ternary Systems at Low Temperatures, Lehigh University, Pennsylvania
M.A.A.M. Salleh, C.M. Gourlay, J.W. Xian, S.A. Belyakov, H. Yasuda, S.D. McDonald, K. Nogita, In situ imaging of microstructure formation in electronic interconnections. Sci. Rep. 7, 1–11 (2017). https://doi.org/10.1038/srep40010
N. Zhao, Y. Zhong, M.L. Huang, H.T. Ma, W. Dong, Growth kinetics of Cu6Sn5 intermetallic compound at liquid-solid interfaces in Cu/Sn/Cu interconnects under temperature gradient. Sci. Rep. 5, 1–12 (2015). https://doi.org/10.1038/srep13491
L. Sun, M. Chen, L. Zhang, Microstructure evolution and grain orientation of IMC in Cu-Sn TLP bonding solder joints. J. Alloys Compd. 786, 677–687 (2019). https://doi.org/10.1016/j.jallcom.2019.01.384
Z.Q. Liu, P.J. Shang, A. D. X. Li, J.K. Shang, Growth kinetics and microstructural evolution of Cu-Sn intermetallic compounds on different Cu substrates during thermal aging, in: Int. Conf. Electron. Packag. Technol. High Density Packag., Beijing, 2009: pp. 569–571. Doi:https://doi.org/10.1109/ICEPT.2009.5270685.
H. Liu, K. Wang, K.E. Aasmundtveit, N. Hoivik, Intermetallic Compound Formation Mechanisms for Cu-Sn Solid – Liquid Interdiffusion Bonding. J. Electron. Mater. 41, 2453–2462 (2012). https://doi.org/10.1007/s11664-012-2060-3
A. Suzuki, Y. Mishin, Atomic mechanisms of grain boundary diffusion: Low versus high temperatures. J. Mater. Sci. 40, 3155–3161 (2005). https://doi.org/10.1007/s10853-005-2678-0
R. Balasubramaniam, Callister’S Materials Science And Engineering: Indian Adaptation (W/Cd) (Wiley India Pvt, Limited, 2009).
H.H. Lou, Y. Huang, Electroplating, in Encycl Chem Process. ed. by H.H. Lou (Taylor and Francis, New York, 2006), pp. 1–10
Y.A. Shen, F.Y. Ouyang, C. Chen, Effect of Sn grain orientation on growth of Cu-Sn intermetallic compounds during thermomigration in Cu-Sn2.3Ag-Ni microbumps. Mater. Lett. 236, 190–193 (2019). https://doi.org/10.1016/j.matlet.2018.10.112
W. Hsu, F. Ouyang, ScienceDirect Effects of anisotropic b -Sn alloys on Cu diffusion under a temperature gradient. Acta Mater. 81, 141–150 (2014). https://doi.org/10.1016/j.actamat.2014.08.029
N.S. Bosco, F.W. Zok, Critical interlayer thickness for transient liquid phase bonding in the Cu–Sn system. Acta Mater. 52, 2965–2972 (2004). https://doi.org/10.1016/j.actamat.2004.02.043
T.T. Luu, A. Duan, K. Wang, K. Aasmundtveit, N. Hoivik, Cu/Sn SLID Wafer-level Bonding Optimization, in: IEEE 63rd Electron. Components Technol. Conf., Las Vegas NV, 2013: pp. 1531–1537. Doi:https://doi.org/10.1109/ECTC.2013.6575775.
Q. Li, Y.C. Chan, Growth kinetics of the Cu3Sn phase and void formation of sub-micrometre solder layers in Sn– Cu binary and Cu–Sn–Cu sandwich structures. J. Alloys Compd. 567, 47–53 (2013). https://doi.org/10.1016/j.jallcom.2013.03.093
R. Huang, H. Ma, S. Shang, A. Kunwar, Y. Wang, H. Ma, Size effect on interface reaction of Sn–xCu/Cu solder joints during multiple reflows. J. Mater. Sci. Mater. Electron. 30, 4359–4369 (2019). https://doi.org/10.1007/s10854-019-00758-7
J. Fan, T. Shi, Z. Tang, B. Gong, J. Li, J. Huang, T. Li, Low-Temperature Cu-Cu Bonding Process Based on the Sn-Cu Multilayer and Self-Propagating Reaction Joining. J. Electron. Mater. 48, 1310–1317 (2019). https://doi.org/10.1007/s11664-018-6827-z
H.J. Van De Wiel, A.B. Vardøy, G. Hayes, H.R. Fischer, A. Lapadatu, M.M. V Taklo, Characterization of hermetic wafer-level Cu-Sn SLID bonding, in: Electron. Syst. Technol. Conf., IEEE, Amsterdam, Netherlands, 2012: pp. 1–7. Doi:https://doi.org/10.1109/ESTC.2012.6542150.
P. Borgesen, L. Yin, P. Kondos, Assessing the risk of Kirkendall voiding in Cu3Sn. Microelectron. Reliab. 51, 837–846 (2011). https://doi.org/10.1016/j.microrel.2010.11.014
A.D. Smigelskas, E.O. Kirkendall, Zinc Diffusion in Alpha Brass. Trans. AIME. 171, 130–142 (1947)
A. Paul, M.J.H. Van Dal, A.A. Kodentsov, F.J.J. Van Loo, The Kirkendall Effect in Multiphase Diffusion. Acta Mater. 52, 623–630 (2004)
K.E. Aasmundtveit, T. Luu, K. Wang, N. Hoivik, Void Formation in Cu – Sn Solid-Liquid Interdiffusion ( SLID ) Bonding, in: Eur. Microelectron. Packag. Conf., 2015: pp. 1–6. /https://ieeexplore.ieee.org/abstract/document/7390754.
P. Borgesen, L. Yin, P. Kondos, D.W. Henderson, G. Servis, J. Therriault, J. Wang, K. Srihari, Sporadic Degradation in Board Level Drop Reliability - Those Aren’t All Kirkendall Voids!, in: Electron. Components Technol. Conf., 2007: pp. 136–146. Doi:https://doi.org/10.1109/ECTC.2007.373788.
G. Ross, V. Vuorinen, M. Paulasto-kröckel, Void Formation in Cu-Sn Micro-Connects, in: Electron. Components Technol. Conf., IEEE, San Diego, CA, 2015: pp. 2193–2199. Doi:https://doi.org/10.1109/ECTC.2015.7159907.
C. Hang, Y. Tian, R. Zhang, Phase transformation and grain orientation of Cu – Sn intermetallic compounds during low temperature bonding process. J. Mater. Sci. Mater. Electron. 24, 3905–3913 (2013). https://doi.org/10.1007/s10854-013-1337-5
J. Yu, J.Y. Kim, Effects of residual S on Kirkendall void formation at Cu/Sn–3.5Ag solder joints. Acta Mater. 56, 5514–5523 (2008). https://doi.org/10.1016/j.actamat.2008.07.022
L. Yin et. al, Controlling Cu Electroplating to Prevent Sporadic Voiding in Cu3Sn, in Electron. Components Technol. Conf., 2009: 406–414. Doi:https://doi.org/10.1109/ECTC.2009.5074046.
M. Onishi, H. Fujibuchi, Reaction Diffusion in Cu Sn System. Trans. Japan Inst. Met. 16, 539–547 (1975). https://doi.org/10.2320/matertrans1960.16.539
G. Ross, H. Xu, V. Vuorinen, M. Paulasto-kröckel, Void Formation in Cu-Sn SLID Bonding for MEMS, in: Electron. Syst. Technol. Conf., IEEE, Helsinki, 2014: pp. 1–3. Doi:https://doi.org/10.1109/ESTC.2014.6962843.
J.Y. Kim, J. Yu, Effects of residual impurities in electroplated Cu on the Kirkendall void formation during soldering. Appl. Phys. Lett. 92, 2006–2009 (2008). https://doi.org/10.1063/1.2890072
V.A. Baheti, P. Kumar, A. Paul, Effect of Au, Pd and Pt addition in Cu on the growth of intermetallic compounds and the Kirkendall voids in the Cu–Sn system. J. Mater. Sci. Mater. Electron. 28, 17014–17019 (2017). https://doi.org/10.1007/s10854-017-7624-9
J. Chen, J. Yang, Y. Zhang, Z. Yu, P. Zhang, Effect of substrates on the formation of Kirkendall voids in Sn/Cu joints. Weld. World. 63, 751–757 (2019). https://doi.org/10.1007/s40194-019-00704-5
J.Y. Song, J. Yu, T.Y. Lee, Effects of reactive diffusion on stress evolution in Cu-Sn films. Scr. Mater. 51, 167–170 (2004). https://doi.org/10.1016/j.scriptamat.2004.03.032
T. Tian, K. Chen, A.A. Macdowell, D. Parkinson, Y. Lai, K.N. Tu, Quantitative X-ray microtomography study of 3-D void growth induced by electromigration in eutectic SnPb flip-chip solder joints. Scr. Mater. 65, 646–649 (2011). https://doi.org/10.1016/j.scriptamat.2011.07.002
C.Y. Liu, J.T. Chen, Y.C. Chuang, L. Ke, S.J. Wang, Electromigration-induced Kirkendall voids at the Cu/Cu3Sn interface in flip-chip Cu/Sn/Cu joints. Appl. Phys. Lett. 90, 3–6 (2007). https://doi.org/10.1063/1.2714100
L. Qu, H.T. Ma, H.J. Zhao, A. Kunwar, N. Zhao, In situ study on growth behavior of interfacial bubbles and its effect on interfacial reaction during a soldering process. Appl. Surf. Sci. 305, 133–138 (2014). https://doi.org/10.1016/j.apsusc.2014.03.003
L. Yin, P. Borgesen, On the root cause of Kirkendall voiding in. J. Mater. Res. 26, 455–466 (2016). https://doi.org/10.1557/jmr.2010.47
H. Li, R. An, C. Wang, B. Li, Suppression of void nucleation in Sn3.0Ag0.5Cu/CU solder joint by rapid thermal processing. Mater. Lett. 158, 252–254 (2015). https://doi.org/10.1016/j.matlet.2015.05.132
S.H. Kim, J. Yu, Heat-treatment to suppress the formation of Kirkendall voids in Sn-3.5Ag/Cu solder joints. Mater. Lett. 106, 75–78 (2013). https://doi.org/10.1016/j.matlet.2013.05.019
I. Panchenko, J. Grafe, M. Mueller, K.J. Wolter, “Effects of bonding pressure on quality of SLID interconnects”, in 2012 4th Electronic System-Integration Technology Conference. ESTC 2012, 1–7 (2012)
I. Panchenko, K. Croes, I. De Wolf, J. De Messemaeker, E. Beyne, K.J. Wolter, Degradation of Cu6Sn5 intermetallic compound by pore formation in solid-liquid interdiffusion Cu/Sn microbump interconnects. Microelectron. Eng. 117, 26–34 (2014). https://doi.org/10.1016/j.mee.2013.12.003
X. Liu, S. He, H. Nishikawa, Low temperature solid-state bonding using Sn-coated Cu particles for high temperature die attach. J. Alloys Compd. 695, 2165–2172 (2017). https://doi.org/10.1016/j.jallcom.2016.11.064
H.K. Kannojia, P. Dixit, Experimental investigations in the intermetallic and microvoid formation in sub-200 °C Cu–Sn bonding. J. Mater. Sci. Mater. Electron, 30, 16427–16438 (2019). https://doi.org/10.1007/s10854-019-02017-1
H.K. Kannojia, P. Dixit, Void formation in Low-temperature Electroplated Cu-Sn stack for Hermetic Packaging, in: Electron. Packag. Technol. Conf., 2019: pp. 124–128. Doi:1109/EPTC47984.2019.9026664.
A. Rautiainen, H. Xu, E. Österlund, J. Li, V. Vuorinen, M. Paulasto-Kröckel, Microstructural Characterization and Mechanical Performance of Wafer-Level SLID Bonded Au-Sn and Cu-Sn Seal Rings for MEMS Encapsulation. J. Electron. Mater. 44, 4533–4548 (2015). https://doi.org/10.1007/s11664-015-3929-8
F. Forsberg, A. Lapadatu, G. Kittilsland, S. Martinsen, N. Roxhed, A.C. Fischer, G. Stemme, B. Samel, P. Ericsson, N. Hoivik, T. Bakke, M. Bring, T. Kvisteroy, A. Ror, F. Niklaus, CMOS-integrated Si/SiGe quantum-well infrared microbolometer focal plane arrays manufactured with very large-scale heterogeneous 3-D integration. IEEE J. Sel. Top. Quantum Electron. 21, 30–40 (2015). https://doi.org/10.1109/JSTQE.2014.2358198
V. Vuorinen, G. Ross, H. Viljanen, J. Decker, M. Paulasto-Krockel, Process Integration and Reliability of Wafer Level SLID Bonding for Poly-Si TSV capped MEMS, in: Electron. Syst. Technol. Conf., Dresden, 2018: pp. 1–6. Doi:https://doi.org/10.1109/ESTC.2018.8546398.
A. Kaiser, D. Kueck, P. Benkart, A. Munding, G.M. Prinz, A. Heittmann, H. Huebner, R. Sauer, E. Kohn, Concept for diamond 3-D integrated UV sensor. Diam. Relat. Mater. 15, 1967–1971 (2006). https://doi.org/10.1016/j.diamond.2006.07.012
J.Y. Shih, Y.C. Chen, C.H. Chiu, Y.C. Hu, C.L. Lo, C.C. Chang, K.N. Chen, Advanced TSV-based crystal resonator devices using 3-d integration scheme with hermetic sealing. IEEE Electron Device Lett. 34, 1041–1043 (2013). https://doi.org/10.1109/LED.2013.2265335
Z. Wu, J. Cai, Q. Wang, J. Wang, D. Wang, Wafer-Level Hermetic Package by Low-Temperature Cu/Sn TLP Bonding with Optimized Sn Thickness. J. Electron. Mater. 46, 6111–6118 (2017). https://doi.org/10.1007/s11664-017-5546-1
R. Wieland, D. Bonfert, A. Klumpp, R. Merkel, L. Nebrich, J. Weber, P. Ramm, 3D Integration of CMOS transistors with ICV-SLID technology. Microelectron. Eng. 82, 529–533 (2005). https://doi.org/10.1016/j.mee.2005.07.052
H.K. Kannojia, J. Arab, R. Kumar, J. Pednekar, P. Dixit, Formation of Through-Wafer 3-D interconnects in Fused Silica Substrates by Electrochemical Discharge Machining, in: Electron. Packag. Technol. Conf., 2019: pp. 253–257. Doi:https://doi.org/10.1109/EPTC47984.2019.9026625.
Y. Lv, M. Chen, M. Cai, S. Liu, A reliable Cu-Sn stack bonding technology for 3D-TSV packaging. Semicond. Sci. Technol. 29, 025003 (2014). https://doi.org/10.1088/0268-1242/29/2/025003
L.C. Shen, C.W. Chien, H.C. Cheng, C.T. Lin, Development of three-dimensional chip stacking technology using a clamped through-silicon via interconnection. Microelectron. Reliab. 50, 489–497 (2010). https://doi.org/10.1016/j.microrel.2009.10.012
Y. Cao, W. Ning, L. Luo, Wafer-level package with simultaneous TSV connection and cavity hermetic sealing by solder bonding for MEMS device. IEEE Trans. Electron. Packag. Manuf. 32, 125–132 (2009). https://doi.org/10.1109/TEPM.2009.2021766
Y.C. Hu, Y.C. Huang, P.T. Huang, S.L. Wu, H.C. Chang, Y.T. Yang, Y.H. You, J.M. Chen, Y.Y. Huang, Y.H. Lin, J.R. Duann, T.W. Chiu, W. Hwang, C. Te Chuang, J.C. Chiou, K.N. Chen, An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem. IEEE Trans. Electron Devices. 64, 1666–1673 (2017). https://doi.org/10.1109/TED.2017.2660763
Funding
The authors like to acknowledge the financial support from the Industrial Research and Consulting Center (IRCC), Indian Institute of Technology (IIT) Bombay, India, under the seed grant project (RD/0515-IRCCSH0-010 (15IRCCSG002)). The authors are also thankful to the fabrication facility at the Center of Excellence in Nanoelectronics (CEN), IIT Bombay.
Author information
Authors and Affiliations
Contributions
HK planned and carried out the experiments and written the manuscript. PD secured the research funding, reviewed the experimental plan, analyzed the results and reviewed the manuscript.
Corresponding author
Ethics declarations
Conflict of interest
The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.
Ethical approval
The manuscript is prepared as per the researcher’s ethics.
Consent for publication
The authors provide their consent for publication of this manuscript.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Kannojia, H.K., Dixit, P. A review of intermetallic compound growth and void formation in electrodeposited Cu–Sn Layers for microsystems packaging . J Mater Sci: Mater Electron 32, 6742–6777 (2021). https://doi.org/10.1007/s10854-021-05412-9
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10854-021-05412-9