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Drain Current and Transconductance Analysis of Double-Gate Vertical Doped Layer TFET

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Micro-Electronics and Telecommunication Engineering (ICMETE 2023)

Part of the book series: Lecture Notes in Networks and Systems ((LNNS,volume 894))

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Abstract

Due to its sharp subthreshold swing and low leakage current, VDL-TFET has become a potential option for low-power electronic devices. In this study, we examine the influence of various device settings on the electrical properties of VDL-TFETs to assess their performance in low-power applications. We analysis how the doping level, layer thickness, gate length, and temperatures affect the functionality of VDL-TFETs. Simulations conducted by us demonstrate that by carefully tuning those parameters, the device’s ON-current, subthreshold swing, and delay properties may be greatly enhanced, rendering it appropriate for low-power digital and analogue electronics. We additionally contrast the efficiency of VDL-TFETs against that of various other low-power transistors, including FinFETs, and show that the subthreshold swing and delay features of VDL-TFETs are comparable to those of FinFETs. According to our research, VDL-TFETs are an intriguing technology for low-power semiconductor purposes.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Dr. B. R. Ambedkar National Institute of Technology, Jalandhar, Punjab, India

    Mandeep Singh, Nakkina Sai Teja, Tarun Chaudhary, Balwinder Raj & Deepti Kakkar

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  1. Mandeep Singh
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  2. Nakkina Sai Teja
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  3. Tarun Chaudhary
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  4. Balwinder Raj
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  5. Deepti Kakkar
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Correspondence to Mandeep Singh .

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Editors and Affiliations

  1. Department of Electronics and Communication Engineering, ABES Engineering College, Ghaziabad, Uttar Pradesh, India

    Devendra Kumar Sharma

  2. National Taipei University of Business, Taoyuan, Taiwan

    Sheng-Lung Peng

  3. Department of Electronics and Communication Engineering, ABES Engineering College, Ghaziabad, Uttar Pradesh, India

    Rohit Sharma

  4. Department of Embedded Systems Engineering, Incheon National University, Incheon, Korea (Republic of)

    Gwanggil Jeon

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Singh, M., Teja, N.S., Chaudhary, T., Raj, B., Kakkar, D. (2024). Drain Current and Transconductance Analysis of Double-Gate Vertical Doped Layer TFET. In: Sharma, D.K., Peng, SL., Sharma, R., Jeon, G. (eds) Micro-Electronics and Telecommunication Engineering. ICMETE 2023. Lecture Notes in Networks and Systems, vol 894. Springer, Singapore. https://doi.org/10.1007/978-981-99-9562-2_3

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  • DOI: https://doi.org/10.1007/978-981-99-9562-2_3

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  • Print ISBN: 978-981-99-9561-5

  • Online ISBN: 978-981-99-9562-2

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