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Simulation and Analysis of Graded-Channel Dual-Insulator Double-Gate Junction-Less FET

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Proceedings of Integrated Intelligence Enable Networks and Computing

Part of the book series: Algorithms for Intelligent Systems ((AIS))

Abstract

In this paper, a Si/SiGe graded-channel (GC) dual-insulator (DI) double-gate (DG) junction-less (JL) FET is presented. The proposed GC-DI-DG-JL FET is studied using 2D simulations to analyse the effect of gate metal workfunction (\(\phi _m\)) variation in switching performance parameters. The increment in \(\phi _m\) fully depletes the channel under OFF-state which improves the subthreshold characteristics of the proposed device. So that the proposed structure is benefited with the significant improvement in SS, DIBL and \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) by increasing \(\phi _m\). For an optimised value of \(\phi _m\), the GC-DI-DG-JL FET offers the SS of \(70\ {\mathrm{mV/dec}}\), \(V_t\) of \(0.83\ V\), \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) of \(\sim 10^{12}\) and DIBL of \(45\ {\mathrm{mV/V}}\).

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Authors and Affiliations

  1. Vivo India Pvt Ltd, Greater Noida, UP, India

    Rajendra Joshi

  2. G B Pant Institute of Engineering and Technology, Pauri Garhwal, UK, India

    Tripuresh Joshi & Sandeep Kumar

Authors
  1. Rajendra Joshi
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  2. Tripuresh Joshi
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  3. Sandeep Kumar
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Corresponding author

Correspondence to Tripuresh Joshi .

Editor information

Editors and Affiliations

  1. Department of Mechanical Engineering, Govind Ballabh Pant Institute of Engineering & Technology, Pauri Garhwal, Uttarakhand, India

    Krishan Kant Singh Mer

  2. Department of Computer Science and Engineering, Maulana Azad National Institute of Technology, Bhopal, India

    Vijay Bhaskar Semwal

  3. Department of Electronics and Communication, Institute of Technology Gopeshwar, Gopeshwar, India

    Vishwanath Bijalwan

  4. Universidad Internacional de La Rioja, Logroño, Spain

    Rubén González Crespo

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Joshi, R., Joshi, T., Kumar, S. (2021). Simulation and Analysis of Graded-Channel Dual-Insulator Double-Gate Junction-Less FET. In: Singh Mer, K.K., Semwal, V.B., Bijalwan, V., Crespo, R.G. (eds) Proceedings of Integrated Intelligence Enable Networks and Computing. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-33-6307-6_59

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