Abstract
In this paper Schmitt trigger based three different static random access memory bit cells–7, 9 and 10 T–are designed at a 32 nm technology node and their results are analyzed. The static noise margin obtained for 7, 9, and 10 T SRAM bit cells for hold operation are–22, 131, and 126 mV respectively. While, for the read operation the noise margin values are–22, 131, and 27 mV respectively. The dynamic write analysis reveals that the 9 T SRAM cell has a minimal pulse width requirement of 35 ns for a successful write operation. These cache memories are subject to temperature variation operation. Therefore, the Schmitt trigger based bit cells are analyzed by varying temperatures from −10 to 110 ℃. The temperature variation analysis demonstrates 10 T SRAM cell has the least variation in static performance. Another parameter used to compare the performance of the cells is leakage current. This identifies 9 T SRAM bit cell has the maximum leakage current with 635 pA and 630 pA for Q = ‘0’ and ‘1’ respectively.
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References
Calhoun, B., & Chandrakasan, A. (2006). Static noise margin variation for sub-threshold SRAM in 65-nm CMOS. IEEE Journal on Solid-State Circuits, 41(7), 1673–1679.
Toh, S. O., Guo, Z., Liu, T. J. K., & Nikolic, B. (2011). Characterization of dynamic SRAM stability in 45nm CMOS. IEEE Journal on Solid-State Circuits, 46(11), 2702–2712.
Rawat, G., Rathore, K., Goyal, S., Kala, S., & Mittal, P. (2015). Design and analysis of ALU: Vedic mathematics approach. In International Conference on Computing, Communication & Automation (pp. 1372–1376).
Chang, M. H., Chiu, Y. T., & Hwang, W. (2012). Design and iso-area Vmin analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65-nm CMOS. IEEE Transactions on Circuits Systems II: Express Briefs, 59(7), 429–433.
Chang, I. J., Kim, J. J., Park, S. P., & Roy, K. (2009). A 32 kb 10T subthreshold SRAM cell array with bit-interleaving and differential read scheme in 90 nm CMOS. IEEE Journal on Solid-State Circuits, 44(2), 650–658.
Chang, L., Montoye, R. K., Nakamura, Y., Batson, K. A., Eickemeyer, R. J., Dennard, R. H., Haensch, W., & Jamsek, D. (2008). An 8T-SRAM for variability tolerance and low-voltage operation in high-performance caches. IEEE Journal on Solid-State Circuits., 43(4), 956–963.
Pasandi, G., & Fakhraie, S. M. (2015). A 256-kb 9T near-threshold SRAM with 1k cells per bitline and enhanced write and read operations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(11), 2438–2446.
Rawat, B., & Mittal, P. (2021). Single bit line accessed high high performance ultra low voltage operating 7T SRAM bit cell with improved read stability. International Journal of Circuit Theory and Application, 49(5), 1435–1449.
Ahmad, S., Gupta, M. K., Alam, N., & Hasan, M. (2016). Single-ended Schmitt-trigger-based robust low-power SRAM cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2634–2642.
Mishra, N., Mittal, P., & Kumar, B. (2019). Analytical modeling for static and dynamic response of organic pseudo all-p inverter circuits. Journal of Computational Electronics., 18(4), 1490–1500.
Mukhopadhyay, S., Mahmoodi, H., & Roy, K. (2005) Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. IEEE Transactions on Computer Aided Design (CAD) Integrated Circuits Systems, 24(12), 1859–1880.
Yoshinobu, N., Masahi, H., Takayuki, K., & Itoh, K. (2003). Review and future prospects of low-voltage RAM circuits. IBM Journal for Research and Development, 47(5/6), 525–552.
Kumar, N., Mittal, P. (2020). Performance analysis of FinFET based 2:1 multiplexers for low power application. In 6th Students’ Conference on Engineering and Systems.
Rabaey, J., Chandrakasan, A., & Nikolic, B. (2002). Digital integrated circuits: A design perspective (2nd ed.). Prentice-Hall.
Singh, J., Mohanty, S. P., & Pradhan, D. K. (2013). Robust SRAM designs and analysis. Springer.
Kulkarni, J. P., & Roy, K. (2012). Ultralow-voltage process-variation-tolerant schmitt-trigger-based SRAM design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 319–332.
Zhang, A., Srivastava, A., & Ajmera, P. K. (2003). Low voltage CMOS schmitt trigger circuit. Electron Letters, 39(24), 1696–1698.
Sanapala, K. R. S., Yeo, S. S. (2018). Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) Applications. Journal of Supercomputing, 74, 4613–4622.
Raj, K., Kumar, B., & Mittal, P. (2009). FPGA implementation and mask level CMOS layout design of redundant binary signed digit comparator. IJCSNS, 9(9), 107.
Cho, K., Park, J., Oh, T. W., & Jung, S. O. (2020). One-sided Schmitt Trigger Based 9T SRAM Cell for Near Threshold Operation. IEEE Transaction on Circuits and Systems I: Regular Papers., 67(5), 1551–1561.
Kulkarni, J., Kim, K., & Roy, K. (2007). A 160 mV robust Schmitt trigger based sub-threshold SRAM cell. IEEE Journal on Solid-State Circuits, 42(10), 2303–2313.
Rawat, B., & Mittal, P. (2021) Single bit line accessed high performance ultra low voltage operating 7-T SRAM cell with improved read stability. Semiconductor Science and Technology, 36(9).
Kang, S., Leblebici, Y., Kim, C. (2015). CMOS digital integrated circuits (3rd ed., pp. 204–422). McGraw-Hill.
Rawat, B., Gupta, K., & Goel, N. (2018). Low voltage 7T SRAM bit cell in 32 nm CMOS technology node. In 2018 International Conference of Computing, Power, and Communications Technologies (GUCON).
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Rawat, B., Mittal, P. (2023). Investigating the Impact of Schmitt Trigger on SRAM Cells at 32 nm Technology Node for Low Voltage Applications. In: Darji, A.D., Joshi, D., Joshi, A., Sheriff, R. (eds) Advances in VLSI and Embedded Systems. Lecture Notes in Electrical Engineering, vol 962. Springer, Singapore. https://doi.org/10.1007/978-981-19-6780-1_5
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DOI: https://doi.org/10.1007/978-981-19-6780-1_5
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