Abstract
In this article, a Schmitt trigger based 12-Transistors(ST12T) static random-access memory (SRAM) bit-cell has been proposed. The Read Power of proposed cell is reduced by 29.17%/ 24.14% /7.66% /5.87% /7.67% /16.62% when compared to 6T/ 7T/ TA8T/ 9T/ PPN10T/ D2p11T SRAM cells. Proposed ST12T cell also shows 1.52\(\times\) and 1.86\(\times\) lesser variability in read current and read power respectively as compared to conventional 6T SRAM cell. Further, the write access time/read access time of the proposed topology are improved by \(1.71 \times /1.82 \times\) as compared to 6T SRAM cell. The read power delay product of proposed ST12T cell is minimum with variation in supply voltage from 0.5 to 1 V when compared with all considered SRAM cells. ST12T SRAM cell also exhibits 26.82% and 8.87% higher read static noise margin and write static noise margin respectively as compared to conventional 6T SRAM cell. This may be attributed to Schmitt trigger design of inverters in core latch of proposed SRAM cell. The proposed bit-cell is free from half select issue and supports bit interleaving format. Authors have used cadence virtuoso tool with Generic Process Design Kit 45 nm technology file to carry out simulation.
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig1_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig2_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig3_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig4_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig5_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig6_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig7_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig8_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig9_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig10_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig11_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig12_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig13_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig14_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig15_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig16_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig17_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig18_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig19_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig20_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig21_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig22_HTML.png)
![](http://media.springernature.com/m312/springer-static/image/art%3A10.1007%2Fs10470-020-01718-6/MediaObjects/10470_2020_1718_Fig23_HTML.png)
Similar content being viewed by others
References
Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992). Low-power cmos digital design. IEICE Transactions on Electronics, 75(4), 371.
Nakagome, Y., Horiguchi, M., Kawahara, T., & Itoh, K. (2003). Review and future prospects of low-voltage ram circuits. IBM Journal of Research and Development, 47(5.6), 525.
Bhavnagarwala, A. J., Tang, X., & Meindl, J. D. (2001). The impact of intrinsic device fluctuations on cmos sram cell stability. IEEE Journal of Solid-State Circuits, 36(4), 658.
Flynn, M. J., & Luk, W. (2011). Computer system design: system-on-chip. Hoboken: Wiley. https://doi.org/10.1002/9781118009925.ch2.
Mukhopadhyay, S., Mahmoodi, H., & Roy, K. (2005). Modeling of failure probability and statistical design of sram array for yield enhancement in nanoscaled cmos. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(12), 1859.
Raychowdhury, A., Mukhopadhyay, S., & Roy, K. (2005). A feasibility study of subthreshold sram across technology generations. In 2005 International conference on computer design (pp. 417–422). IEEE.
Kawaguchi, H., Itaka, Y., & Sakurai, T. (1998). Dynamic leakage cut-off scheme for low-voltage sram’s. In 1998 Symposium on VLSI circuits. Digest of Technical Papers (Cat. No. 98CH36215) (IEEE, pp. 140–141).
Gupta, R., & Dasgupta, S. (2019). Process corners analysis of data retention voltage (drv) for 6t, 8t, and 10t sram cells at 45 nm. IETE Journal of Research, 65(1), 114.
Qin, H., Cao, Y., Markovic, D., Vladimirescu, A., & Rabaey, J. (2005). Standby supply voltage minimization for deep sub-micron sram. Microelectronics Journal, 36(9), 789.
Farkhani, H., Peiravi, A., & Moradi, F. (2014). A new asymmetric 6t sram cell with a write assist technique in 65 nm cmos technology. Microelectronics Journal, 45(11), 1556.
Chang, M. F., Wu, J. J., Chen, K. T., Chen, Y. C., Chen, Y. H., Lee, R., et al. (2010). A differential data-aware power-supplied (d2ps) 8t sram cell with expanded write/read stabilities for lower vddmin applications. IEEE Journal of Solid-State Circuits, 45(6), 1234.
Kushwah, C., & Vishvakarma, S. K. (2015). A single-ended with dynamic feedback control 8t subthreshold sram cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(1), 373.
Yadav, N., Shah, A. P., & Vishvakarma, S. K. (2017). Stable, reliable, and bit-interleaving 12t sram for space applications: A device circuit co-design. IEEE Transactions on Semiconductor Manufacturing, 30(3), 276.
Upadhyay, P., Kar, R., Mandal, D., & Ghoshal, S. P. (2015). A design of low swing and multi threshold voltage based low power 12t sram cell. Computers & Electrical Engineering, 45, 108.
Ahmad, S., Gupta, M. K., Alam, N., & Hasan, M. (2017). Low leakage single bitline 9 t (sb9t) static random access memory. Microelectronics Journal, 62, 1.
Liu, Z., & Kursun, V. (2008). Characterization of a novel nine-transistor sram cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 16(4), 488.
Ansari, M., Afzali-Kusha, H., Ebrahimi, B., Navabi, Z., Afzali-Kusha, A., & Pedram, M. (2015). A near-threshold 7t sram cell with high write and read margins and low write time for sub-20 nm finfet technologies. Integration, 50, 91.
Pasandi, G., & Fakhraie, S. M. (2014). An 8t low-voltage and low-leakage half-selection disturb-free sram using bulk-cmos and finfets. IEEE Transactions on Electron Devices, 61(7), 2357.
Verma, N., & Chandrakasan, A. P. (2008). A 256 kb 65 nm 8t subthreshold sram employing sense-amplifier redundancy. IEEE Journal of Solid-State Circuits, 43(1), 141.
Wen, L., Li, Z., & Li, Y. (2012). Differential-read 8t sram cell with tunable access and pull-down transistors. Electronics Letters, 48(20), 1260.
Cmr, P., & Singh, A. K. (2010). Novel eight-transistor sram cell for write power reduction. IEICE Electronics Express, 7(16), 1175.
Limachia, M. J., Thakker, R. A., & Kothari, N. J. (2018). Characterization of a novel 10t sram cell with improved data stability and delay performance for 20-nm tri-gated finfet technology. Circuit World, 44(4), 187.
Chang, I. J., Kim, J. J., Park, S. P., & Roy, K. (2009). A 32 kb 10t sub-threshold sram array with bit-interleaving and differential read scheme in 90 nm cmos. IEEE Journal of Solid-State Circuits, 44(2), 650.
Mansore, S., & Gamad, R. (2018). A data-aware write-assist 10t sram cell with bit-interleaving capability. Turkish Journal of Electrical Engineering & Computer Sciences, 26(5)
Gavaskar, K., & Ragupathy, U. (2019). Low power self-controllable voltage level and low swing logic based 11t sram cell for high speed cmos circuits. Analog Integrated Circuits and Signal Processing, 100(1), 61.
Lo, C. H., & Huang, S. Y. (2011). Ppn based 10t sram cell for low-leakage and resilient subthreshold operation. IEEE Journal of Solid-State Circuits, 46(3), 695.
Sanvale, P., Gupta, N., Neema, V., Shah, A. P., & Vishvakarma, S. K. (2019). An improved read-assist energy efficient single ended ppn based 10t sram cell for wireless sensor network. Microelectronics Journal, 92, 104611.
Sharma, V., Gopal, M., Singh, P., Vishvakarma, S. K., & Chouhan, S. S. (2019). A robust, ultra low-power, data-dependent-power-supplied 11t sram cell with expanded read/write stabilities for internet-of-things applications. Analog Integrated Circuits and Signal Processing, 98(2), 331.
Gupta, S., Gupta, K., & Pandey, N. (2017). A 32-nm subthreshold 7t sram bit cell with read assist. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(12), 3473.
Ahmad, S., Gupta, M. K., Alam, N., & Hasan, M. (2016). Single-ended schmitt-trigger-based robust low-power sram cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(8), 2634.
Cho, K., Park, J., Oh, T. W., & Jung, S. O. (2020). One-sided schmitt-trigger-based 9t sram cell for near-threshold operation. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(5), 1551.
Yamaoka, M., Maeda, N., Shinozaki, Y., Shimazaki, Y., Nii, K., Shimada, S., Yanagisawa, K., & Kawahara, T. (2005). Low-power embedded sram modules with expanded margins for writing. In ISSCC. 2005 IEEE international digest of technical papers. Solid-state circuits conference, 2005 (pp. 480–611). IEEE.
Kulkarni, J. P., Kim, K., & Roy, K. (2007). A 160 mv robust schmitt trigger based subthreshold sram. IEEE Journal of Solid-State Circuits, 42(10), 2303.
Zaman, H., Wu, X., Zheng, X., Khan, S., & Ali, H. (2018). Suppression of switching crosstalk and voltage oscillations in a sic mosfet based half-bridge converter. Energies, 11(11), 3111.
Kulkarni, J. P., & Roy, K. (2011). Ultralow-voltage process-variation-tolerant schmitt-trigger-based sram design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20(2), 319.
Jahinuzzaman, S. M., Sharifkhani, M., & Sachdev, M. (2009). An analytical model for soft error critical charge of nanometric srams. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 17(9), 1187.
MacKay, D. J. (2003). Information theory, inference and learning algorithms. Cambridge: Cambridge University Press.
Hillier, C., & Balyan, V. (2019). Error detection and correction on-board nanosatellites using hamming codes. Journal of Electrical and Computer Engineering.
Pasandi, G., & Pedram, M. (2018). Internal write-back and read-before-write schemes to eliminate the disturbance to the half-selected cells in srams. IET Circuits, Devices & Systems, 12(4), 460.
Pal, S., & Islam, A. (2015). Variation tolerant differential 8t sram cell for ultralow power applications. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(4), 549.
Seevinck, E., List, F. J., & Lohstroh, J. (1987). Static-noise margin analysis of mos sram cells. IEEE Journal of Solid-State Circuits, 22(5), 748.
Islam, A., & Hasan, M. (2012). Leakage characterization of 10t sram cell. IEEE Transactions on Electron Devices, 59(3), 631.
Sachdeva, A., & Tomar, V. (2020). Design of a stable low power 11-t static random access memory cell. Journal of circuits, Systems and Computers, 2050206.
Dasgupta, S., et al. (2017). 6t sram cell analysis for drv and read stability. Journal of Semiconductors, 38(2), 025001.
Ibrahim, S. N. (2017). Effect of temperature on silicon carriers mobilities using matlab. Al-Mustansiriyah Journal of Science, 28(3), 214.
Islam, A., & Hasan, M. (2012). A technique to mitigate impact of process, voltage and temperature variations on design metrics of sram cell. Microelectronics Reliability, 52(2), 405.
Zhang, K., Bhattacharya, U., Chen, Z., Hamzaoglu, F., Murray, D., Vallepalli, N., et al. (2005). A 3-ghz 70-mb sram in 65-nm cmos technology with integrated column-based dynamic power supply. IEEE Journal of Solid-State Circuits, 41(1), 146.
Wang, J., Nalam, S., & Calhoun, B. H. (2008). Analyzing static and dynamic write margin for nanometer srams. In Proceeding of the 13th international symposium on Low power electronics and design (ISLPED’08) (IEEE, 2008) (pp. 129–134).
Takeda, K., Ikeda, H., Hagihara, Y., Nomura, M., & Kobatake, H. (2006). Redefinition of write margin for next-generation sram and write-margin monitoring circuit. In 2006 IEEE international solid state circuits conference-digest of technical papers (IEEE, 2006) (pp. 2602–2611).
Gierczynski, N., Borot, B., Planes, N., & Brut, H. (2007). A new combined methodology for write-margin extraction of advanced sram. In 2007 IEEE international conference on microelectronic test structures (IEEE, 2007) (pp. 97–100).
Dasgupta, S., et al. (2017). Compact analytical model to extract write static noise margin (wsnm) for sram cell at 45-nm and 65-nm nodes. IEEE Transactions on Semiconductor Manufacturing, 31(1), 136.
Singh, J., Mohanty, S. P., & Pradhan, D. K. (2012). Robust SRAM designs and analysis. New York: Springer.
Chandrakasan, A. P., Sheng, S., & Brodersen, R. W. (1992). Low-power cmos digital design. IEEE Journal of Solid-State Circuits, 27(4), 473.
Pasandi, G., & Fakhraie, S. M. (2014). A 256-kb 9t near-threshold sram with 1k cells per bitline and enhanced write and read operations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(11), 2438.
Sachdeva, A., & Tomar, V. (2020). Design of low power half select free 10-t static random access memory cell. Journal of Circuits, Systems and Computers. https://doi.org/10.1142/S0218126621500730.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Sachdeva, A., Tomar, V.K. A Schmitt-trigger based low read power 12T SRAM cell. Analog Integr Circ Sig Process 105, 275–295 (2020). https://doi.org/10.1007/s10470-020-01718-6
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-020-01718-6