Keywords

1 Introduction

One-bit full adder is considered as an important case study of MRL (Memristor Ratio Logic) family [1]. The full adder consists of two half adder, while the half adder can be composed of an exclusive-OR gate and an AND gate. Based on the basic AND gate, OR gate and exclusive-OR gate, we can implement the circuit design of the adder [2].

In order to provide a standard cell design method, the standard cell is a NAND (NOR) logic gate. In a stable state, no current flows out from the output node because the output node of the AND (OR) logic gate is connected to the metal oxide semiconductor gate [3]. In this method, each standard cell needs to have two connections between the complementary metal oxide semiconductor layer and the memristor layer, one for intermediate level conversion and one for output. This method is robust, although it is inefficient in terms of power consumption and area compared with the optimized circuit. In the optimized circuit, CMOS phase inverter is applied only when signal recovery is needed or logic function needs signal inversion.

The research shows that for MRL logic family, linear memristor devices without current threshold is preferred, unlike other digital applications, which need threshold and nonlinearity [4,5,6]. Compared with nonlinear memristor devices, MRL gate based on linear memristor devices has faster speed, smaller size and lower power consumption. Memristor ratio logic series opens opportunities for additional memristor and complementary metal oxide semiconductor integrated circuits and improves logic density [7,8,9,10,11]. This enhancement can provide more computing power for processors and other computing circuits.

2 Design and Implementation of Adder Circuit Based on Memristor and Its SPICE Simulation

The schematic diagram of one-bit full adder used in this case study is shown in Fig. 1 below. One-bit full adder consists of six OR logic gates based on memristor, three AND logic gates based on memristor and four complementary metal oxide semiconductor phase inverters.

According to the schematic diagram of adder circuit in Fig. 1, the circuit can be built by Hspice software for simulation. The adder calculation formula used in this paper is as follows:

$$ S = A \oplus B \oplus C_{IN} $$
(1)
$$ C_{OUT} = A \cdot B + A \oplus B \cdot C_{IN} $$
(2)
Fig. 1.
figure 1

Schematic diagram of adder circuit

Full size image

The practical meanings represented by each item in the above formula are: \({\text{A}}\) stands for summand, \({\text{B}}\) stands for addend, \(C_{IN}\) stands for low carry, \({\text{S}}\) stands for carry, \({\text{C}}_{OUT}\) stands for sum.

2.1 Analysis of Simulation Results

According to the circuit schematic diagram of adder shown in Fig. 1, simulation analysis is carried out by using Hspice. In this scheme, a voltage of 4 V (high level, i.e., 1) is applied to port \({\text{A}}\), a voltage of 0 V (low level, i.e., 0) is applied to port \({\text{B}}\), and a voltage of 3 V (high level, i.e., 1) is applied to \({\text{C}}_{IN}\) as an example to show the simulation results and analyze them.

The truth table of adder is shown in Table 1 below.

Table 1. Truth table of full adder
Full size table

A voltage of 4 V (high level, i.e., 1) is applied to port \({\text{A }}\), and a voltage of 0 V (low level, i.e., 0) is applied to port \({\text{B}}\). The curve of voltage and time of node 1 after the first exclusive-OR gate is shown in the following Fig. 2. It can be seen that when a voltage of 4 V is applied to port \({\text{A }}\) and a low level is applied to port \({\text{B}}\), the curve of voltage and time of node 1 after the first exclusive-OR gate is basically consistent with the curve of output voltage of exclusive-OR gate when a high level and a low level are input above.

Fig. 2.
figure 2

The curve of voltage and time of node 1 after the first exclusive-OR gate when a voltage of 4 V (high level, i.e., 1) is applied to port \({\text{A }}\), and a voltage of 0 V (low level, i.e., 0) is applied to port \({\text{B}}\).

Full size image

When a voltage of 3 V (high level, i.e. 1) is applied to port \({\text{C}}_{IN}\), the curve of output voltage and time of port \({\text{S}}\) is shown in the following Fig. 3. It can be seen that the output voltage of port \({\text{S}}\) decreases continuously from 0.2ns to 1.2ns, and the speed of taking effect is the fastest at 0.7s. In this period, it can be approximately considered that a high-level pulse voltage of 2 V is input from node 1 and a voltage of 3 V is applied to port \({\text{C}}_{IN}\), and the change characteristic curve of the output voltage of port \({\text{S}}\) is basically consistent with the output voltage curve of exclusive-OR gate when two high levels are input above. When 1.72 V is taken as the threshold voltage, the output voltage is equal to 1.72 V, which is regarded as the output low level (0).

Fig. 3.
figure 3

Curve of output voltage and time of port \({\text{S}}\)

Full size image

When a 3 V voltage (high level, i.e., 1) is applied to the \({\text{C}}_{IN}\), the curve of the output voltage and time of port \({\text{C}}_{OUT}\) is shown in the following Fig. 4. It can be seen that the output voltage of port \({\text{C}}_{OUT}\) with 2.11 V remains stable at about 2.11 V during 0.2ns to 1.2ns, which can be regarded as an AND gate inputting a 2 V high level and a 3 V high level. Another AND gate inputs a 4 V high level and a low level, and the output voltages of the two AND gates can be regarded as high level (1) and low level (0) respectively, and then pass through an OR gate to obtain a curve. When 2.11 V is taken as the threshold voltage, the output voltage is equal to 2.11 V, which is regarded as the output high level (1).

Fig. 4.
figure 4

Curve of output voltage and time of port \({\text{C}}_{{\text{OUT}}}\)

Full size image

In other cases, the output level basically meets the requirements of the truth table of the adder, which will not be discussed in this paper.

3 Analysis and Improvement of This Scheme

For the optimization method, when cascaded MRL gates based on memristor are connected, the current can flow from the output node to the input of the next logic gate. In this case, the currents flowing through two memristor devices of one gate are not equal, and the smaller current may drop below the current threshold of memristor devices, resulting in partial switching of logic gates. This phenomenon will reduce the output voltage and may cause the logic to fail after a single logic level.

One method to eliminate possible logic faults is to increase the voltage of high logic state to ensure that all currents in the circuit are greater than the current threshold of the device. The increase of voltage is limited by complementary metal oxide semiconductor process, because high voltage may lead to breakdown of complementary metal oxide semiconductor transistor (for example, drain and leakage of grid induction [12]), and also consume more power.

Another method to eliminate logic faults is to amplify signals with CMOS logic gate to prevent steady-state current leakage and perform signal recovery. In this case study, both methods are used. The voltage increases and the signal recovery is implemented by a complementary metal oxide semiconductor inverter. Note that these signal degradation problems are circuit-related, that is, the degree of signal degradation depends on the logic circuit structure and the parameters of memristor devices.

Memristor ratio logic is a hybrid complementary metal oxide semiconductor memory logic family. Compared with CMOS logic, this logic series uses less chip area. By using the standard cell library composed of NOR and NAND logic gates, the design workload of MRL circuit can be reduced. However, the standard cell limits the flexibility of the design process and the opportunity of saving area. Other optimization criteria, such as increasing the operating voltage and minimizing the number of connections between CMOS and memristor layer, are also possible.

4 Conclusion

In this paper, a one-bit adder is designed with 18 memristors and 4 CMOS phase inverters. The circuit design diagram of the scheme is given, and the principle, design ideas and possible problems of the scheme are introduced. The designed full adder is simulated by Hspice software, and the output voltage values under various conditions are obtained and compared with the truth table. Then, according to the content of the design scheme, the advantages and disadvantages of the scheme are found out, and the shortcomings are optimized and improved.