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Performance Analysis of Gate-Stack Nanoscaled Recessed-S/D SOI-MOSFET for Analog Applications

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Recent Trends in Electronics and Communication (VCAS 2020)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 777))

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Abstract

Fully-Depleted (FD) Silicon-on-Insulator (SOI) MOSFET has been attracting significant attention from the past two decades due to its excellent immunity over short-dimension effects. This paper investigates the short-channel characteristics of gate-stack (GS) triple-metal-gate (TMG) recessed-source/drain (Re-S/D) FD SOI-MOSFET for analog-applications. Furthermore, the suitability of the GS-TMG: Re-S/D FD SOI MOSFET in the analog domain has been examined on the basis of different figure-of-merit metrics, such as; transconductance, transconductance-efficiency-factor, and output-conductance. Simultaneously, the device reliability issues at different temperatures have also been taken under study. All these studies have been carried out on the basis of numerical simulations over TCAD-Silvaco (ATLAS™). The simulation results reveal that the studied nanoscaled GS-TMG: Re-S/D fully-depleted SOI-MOSFET exhibits enhanced immunity over short-dimension-effects with improved transconductance behavior. Also, the device offers switching ratio (Ion/Ioff) of 1011.

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Author information

Authors and Affiliations

  1. Motilal Nehru National Institute of Technology Allahabad, Prayagraj, 211004, India

    Nilesh Anand Srivastava & Ram Awadh Mishra

  2. CASEST, School of Physics, University of Hyderabad, Hyderabad, 500046, India

    Anjali Priya

Authors
  1. Nilesh Anand Srivastava
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  2. Anjali Priya
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  3. Ram Awadh Mishra
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Corresponding author

Correspondence to Nilesh Anand Srivastava .

Editor information

Editors and Affiliations

  1. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, Uttar Pradesh, India

    Amit Dhawan

  2. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, Uttar Pradesh, India

    Vijay Shanker Tripathi

  3. Department of Information and Communication Technology, Atal Bihari Vajpayee Indian Institute of Information Technology and Management, Gwalior, Madhya Pradesh, India

    Karm Veer Arya

  4. Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada

    Kshirasagar Naik

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Srivastava, N.A., Priya, A., Mishra, R.A. (2022). Performance Analysis of Gate-Stack Nanoscaled Recessed-S/D SOI-MOSFET for Analog Applications. In: Dhawan, A., Tripathi, V.S., Arya, K.V., Naik, K. (eds) Recent Trends in Electronics and Communication. VCAS 2020. Lecture Notes in Electrical Engineering, vol 777. Springer, Singapore. https://doi.org/10.1007/978-981-16-2761-3_55

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  • DOI: https://doi.org/10.1007/978-981-16-2761-3_55

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  • Print ISBN: 978-981-16-2760-6

  • Online ISBN: 978-981-16-2761-3

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