Abstract
Lightweight cryptography is a field of cryptography where implementation for resource constrained devices are in big demand. Piccolo is an ultra-lightweight block cipher having block size of 64-bit and key size of 80-bit and 128-bit. Compact implementations becomes more important when they can provide sufficient security without compromise in performance. In this paper an efficient architecture for Piccolo-80 cipher have been proposed. This cipher requires extreamely low area in hardware implementation, and hence it is useful in RFID applications. Piccolo with its proposed architecture has been implemented on various platforms of FPGA.The proposed work shows 112% improvement in terms of area and 17.65% better results in terms of efficiency. Different devices of Virtex and Spartan have been used to get the results.
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Acknowledgements
This work has been carried out under Information Security Education Awareness (ISEA) project phase – II & SMDP-C2SD project funded by Ministry of Electronics and Information Technology (MeitY), Govt. of India in the Department of Electronics and Communication Engineering at National Institute of Technology Raipur, India. Authors are thankful to the Ministry for the facilities provided under this project.
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Mishra, S., Mishra, Z., Acharya, B. (2021). Area Optimized Hardware Architecture of Piccolo-80 Lightweight Block Cipher. In: Nath, V., Mandal, J.K. (eds) Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 748. Springer, Singapore. https://doi.org/10.1007/978-981-16-0275-7_28
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DOI: https://doi.org/10.1007/978-981-16-0275-7_28
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