Abstract
There is a growing concern regarding the increased standby power and reduced stability of SRAM due to continued scaling in technology node. So, there is a necessity to design a new SRAM cell which addresses the concerns related to SRAM cell. So, 10T SRAM cell is proposed with reduced standby power and enhanced stability in read, write and hold modes of operation. There is a reduction in standby power because of the usage of stacked transistors. P10T SRAM cell has decreased the standby power while holding 1 by 4.9%, 15.99% and 1.68% compared to 8T, 8TG and 9T respectively at the worst process corner FF at 0.9 V VDD. There is an increase of 262.89, 47.566, 261.75% write margin compared to 6T, 8TG, 9T SRAM cells at 0.9 V supply voltage for TT corner. The influence of process and voltage variations on write margin was studied on available and proposed SRAM cells. All designs are designed using in cadence virtuoso in 45 nm CMOS technology node.
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Manoj Kumar, R., Sridevi, P.V. (2021). Design of Low Standby Power 10T SRAM Cell with Improved Write Margin. In: Chowdary, P., Chakravarthy, V., Anguera, J., Satapathy, S., Bhateja, V. (eds) Microelectronics, Electromagnetics and Telecommunications. Lecture Notes in Electrical Engineering, vol 655. Springer, Singapore. https://doi.org/10.1007/978-981-15-3828-5_53
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DOI: https://doi.org/10.1007/978-981-15-3828-5_53
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