Abstract
Real-time image processing in the field of computer vision is not only a challenging task, but requires several embedded computing considerations. In the present era, FPGA-based reconfigurable architecture is widely used for its parallel computing compatibility and fast hardware prototyping. In this paper, a 2D convolution operation is applied to the complete image by splitting it into vertical blocks on which row buffering is applied separately without any substantial increase in the buffer storage area. The proposed technique reduces the execution time with each parallelism stage and utilizes lesser hardware resource as compared to other partitioning schemes. As compared to several existing parallelizing scheme for data processing through FPGA, vertical splitting has been found to work promisingly. Additionally, a table indicating the optimum parallelism stages achievable with given timing constraints, memory bandwidth and, available resources is provided.
Sonam Rani and Bipin Koli contributed to this worked in the past during their tenure with CSIR—Central Scientific Instruments Organisation, Chandigarh.
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Poddar, S., Rani, S., Koli, B., Kumar, V. (2020). Area-Efficient Splitting Mechanism for 2D Convolution on FPGA. In: Sharma, H., Pundir, A., Yadav, N., Sharma, A., Das, S. (eds) Recent Trends in Communication and Intelligent Systems. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-15-0426-6_18
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DOI: https://doi.org/10.1007/978-981-15-0426-6_18
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