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Fast buffering for FPGA implementation of vision-based object recognition systems

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Abstract

Real-time frame rate is an important factor for practical deployment of computer vision systems. Field programmable gate array (FPGA) technology has been considered for many applications due to its parallel computing capability. FPGA implementations of computer vision algorithms normally involve buffering data on external memory devices, which could slow down the whole system. This paper proposes a buffering scheme suitable for implementing real-time vision-based systems on an FPGA that does not require external memory to buffer data. A stop sign detection system implemented on an FPGA employing the proposed buffering scheme is presented as an example system. This system is capable of processing over 200 fps at the frame size of 480 × 752 pixels.

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Authors and Affiliations

  1. Department of Electronic Engineering, La Trobe University, Melbourne, Australia

    Tam P. Cao, Darrell Elton & Guang Deng

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  1. Tam P. Cao
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  2. Darrell Elton
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  3. Guang Deng
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Correspondence to Tam P. Cao.

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Cao, T.P., Elton, D. & Deng, G. Fast buffering for FPGA implementation of vision-based object recognition systems. J Real-Time Image Proc 7, 173–183 (2012). https://doi.org/10.1007/s11554-011-0201-1

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  • DOI: https://doi.org/10.1007/s11554-011-0201-1

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