Skip to main content

Impact of Dummy Logic Insertion on Xilinx Family for Hardware Trojan Prevention

  • Conference paper
  • First Online:
Advanced Informatics for Computing Research (ICAICR 2019)

Part of the book series: Communications in Computer and Information Science ((CCIS,volume 1076))

  • 635 Accesses

Abstract

The vogue of globally manufacturing ICs is increasing rapidly due to which the systems are vulnerable to pernicious Trojan. A promising technique is needed to prevent systems from Trojan. The paper proposes a technique to protect system, in which unused spaces are filled with some dummy logic i.e., (any logic that does not interrupt the functioning of main circuitry). The rival could substitute the dummy logic with malicious Trojan. In order to thwart such situation AES encryption of 128 bit length of modified design is done. The proposed technique is implemented on Xilinx 10.1_ISE in family Automatic Sparton3 and device XA3S50 and comparison with other families of Xilinx is done. The modified design provides 100% protection from HT but not at the cost of performance and power penalties. The proposed technique requires same memory as needed by original circuit.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Zhang, J., Yuan, F., Wei, L., Liu, Y., Xu, Q.: VeriTrust: verification for hardware trust. IEEE Trans. Comput. Aided Design Integr. Circ. Syst. 34(7), 1148–1161 (2015)

    Article  Google Scholar 

  2. News live mint. http://www.livemint.com/Industry/lZKRWzBafdcjOM1cZmEOrN/Regin-trojan-spying-on-countries-like-India.html

  3. Mitra, S., Wong, H.S.P., Wong, S.: The Trojan-proof chip. Spectr. IEEE 52(2), 46–51 (2015)

    Article  Google Scholar 

  4. News. https://www.fbi.gov/news/stories/gameover-zeus-botnet-disrupted

  5. Xuan, X., Singh, A.D., Chatterjee, A.: Lifetime prediction and design- for-reliability of IC interconnections with electromigration induced degradation in the presence of manufacturing defects. J. Electron. Test. 22, 471–482 (2006)

    Article  Google Scholar 

  6. Wu, T.F.: TPAD: hardware Trojan prevention and detection for trusted integrated circuits. IEEE Trans. Comput. Aided Design Integr. Circ. Syst. 35, 521–534 (2016)

    Article  Google Scholar 

  7. Salmani, H.: The global integrated circuit supply chain flow and the hardware Trojan attack. Trusted Digital Circuits, pp. 1–11. Springer, Cham (2018). https://doi.org/10.1007/978-3-319-79081-7_1

    Chapter  Google Scholar 

  8. Dong, C., He, G., Liu, X., Yang, Y., Guo, W.: A multi-layer hardware Trojan protection framework for IoT chips. IEEE Access 7, 23628–23639 (2019)

    Article  Google Scholar 

  9. Zarrinchian, G., Zamani, M.S.: Latch-based structure: a high resolution and self-reference technique for hardware Trojan detection. IEEE Trans. Comput. 66, 100–113 (2017)

    Article  MathSciNet  Google Scholar 

  10. Veeranna, N., Schafer, B.: Hardware Trojan detection in behavioral intellectual properties (IPs) using property checking techniques. IEEE Trans. Emerg. Top. Comput. 5, 576–585 (2016)

    Article  Google Scholar 

  11. Salmani, H.: COTD: Reference-free hardware trojan detection and recovery based on controllability and observability in gate-level netlist. IEEE Trans. Inf. Forensics Secur. 12(2), 338–350 (2017)

    Article  Google Scholar 

  12. Fern, N., San, I., Cheng, K.-T.T.: Detecting hardware Trojans in unspecified functionality through solving satisfiability problems. In: 22nd Design Automation Conference (ASP-DAC), IEEE Press, Asia and South Pacific, pp. 598–504 (2017)

    Google Scholar 

  13. Hazra, S., Sattenapalli, J.S., Roy, A., Dalui, M.: Evaluation and detection of hardware Trojan for real-time many-core systems. In: 8th International Symposium on Embedded Computing and System Design (ISED), IEEE Press, Cochin, India, pp. 31–36 (2018)

    Google Scholar 

  14. Khaleghi, B., et al.: FPGA-based protection scheme against hardware Trojan horse insertion using dummy logic. IEEE Embedded Syst. Lett. 7, 46–50 (2015)

    Article  Google Scholar 

  15. Subramani, K.S., Antonopoulos, A., Abotabl, A.A., Nosratinia, A., Makris, Y.: Demonstrating and mitigating the risk of a FEC-based hardware Trojan in wireless networks. IEEE Trans. Inf. Forensics Secur. 14, 2720–2734 (2019)

    Article  Google Scholar 

  16. Xiao, K., Tehranipoor, M.: BISA: built-in self-authentication for preventing hardware Trojan insertion. In: IEEE International Symposium, Hardware-Oriented Security and Trust (HOST), IEEE Press, Austin, TX, pp. 45–50 (2013)

    Google Scholar 

  17. Rithesh, M., Harish, G., Ram, B.V.B., Yellampalli, S.: Detection and analysis of hardware trojan using scan chain method. In: 19th International Symposium on VLSI Design and Test (VDAT), IEEE Press, Ahmedabad, India, pp. 1–6 (2015)

    Google Scholar 

  18. Zhang, J.: A practical logic obfuscation technique for hardware security. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 24, 1193–1197 (2016)

    Article  Google Scholar 

  19. Ziad, T.I., Alanwar, A., Alkabani, Y., El-Kharashi, M.W., Bedour, H.: Homomorphic data isolation for hardware trojan protection. In: IEEE Computer Society Annual Symposium on VLSI, pp. 131–136, IEEE Press, Montpellier, France (2015)

    Google Scholar 

  20. Elgamal, T.: A public key cryptosystem and a signature scheme based on discrete logarithms. IEEE Trans. Inf. Theory 31(4), 469–472 (1985)

    Article  MathSciNet  Google Scholar 

  21. Wei, S., Potkonjak, M.: Self-consistency and consistency-based detection and diagnosis of malicious circuitry. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(9), 1845–1853 (2014)

    Article  Google Scholar 

  22. Shekarian, S.M.H., Zamani, M.S.: Improving hardware Trojan detection by retiming. Microprocess. Microsyst. 39, 145–156 (2015)

    Article  Google Scholar 

  23. Albrecht, C.: IWLS 2005 benchmarks. In: International Workshop for Logic Synthesis (IWLS). http://www.iwls.org

  24. Tehranipoor, M., Karri, R., Koushanfar, F., Potkonjak, M.: TrustHub. https://www.trust-hub

  25. Qu, S., Shou, G., Hu, Y., Guo, Z., Qian, Z.: High throughput, pipelined implementation of AES on FPGA. In: International Symposium on Information Engineering and Electronic Commerce, IEEE Press, Ternopil, Ukraine, pp. 542–545 (2009)

    Google Scholar 

  26. Hoang, T.: An efficient FPGA implementation of the advanced encryption standard algorithm. In: IEEE International Conference on Computing and Communication Technologies, Research, Innovation, and Vision for the Future (RIVF), IEEE Press, Ho Chi Minh City, Vietnam, pp. 1–4 (2012)

    Google Scholar 

  27. Stallings, W.: Cryptography and Network Security, 3rd edn. Pearson, Boston (2017)

    Google Scholar 

  28. Zhang, J., Yuan, F., Wei, L., Sun, Z., Qiang, X.: VeriTrust: verification for hardware trust. IEEE Trans. Comput. Aided Design Integr. Circ. Syst. 34(7), 1148–1161 (2015)

    Article  Google Scholar 

  29. Jin, Y., Makris, Y.: Hardware Trojan detection using path delay fingerprint. In: IEEE International Workshop on Hardware-Oriented Security and Trust, HOST, IEEE Press, USA, pp. 51–57 (2008)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding authors

Correspondence to Anaahat Dhindsa or Sunil Agrawal .

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Brar, N.K., Dhindsa, A., Agrawal, S. (2019). Impact of Dummy Logic Insertion on Xilinx Family for Hardware Trojan Prevention. In: Luhach, A., Jat, D., Hawari, K., Gao, XZ., Lingras, P. (eds) Advanced Informatics for Computing Research. ICAICR 2019. Communications in Computer and Information Science, vol 1076. Springer, Singapore. https://doi.org/10.1007/978-981-15-0111-1_7

Download citation

  • DOI: https://doi.org/10.1007/978-981-15-0111-1_7

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-0110-4

  • Online ISBN: 978-981-15-0111-1

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics