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Plasma-Enhanced Chemical Vapor Deposition of FSG and a-C:F Low-k Materials

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Low Dielectric Constant Materials for IC Applications

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 9))

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Abstract

Although multilevel interconnection technology is a key to the production of high-performance ultra-large-scale integration (ULSI) circuits, the shrinking design rule of ULSI circuits has recently increased the interconnection delay caused by parasitic capacitance so much that this delay has become more of a problem than the gate delay [1]. To reduce this delay, we must reduce the parasitic capacitance of the intermetal dielectrics (IMD) as well as the resistance of the wiring metals. For this reason, a great deal of effort has been spent in developing low dielectric constant (low-κ) materials that can reduce the parasitic capacitance of interconnects in ULSI circuits [2].

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Authors
  1. K. Endo
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  2. K. Kishimoto
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  3. Y. Matsubara
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  4. K. Koyanagi
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Editor information

Editors and Affiliations

  1. Texas Materials Institute, The University of Texas at Austin, Austin, TX, 78712, USA

    Paul S. Ho

  2. Intel Corp., MS: RA1-204, 5200 N.E. Elam Young Parkway, Hillsboro, OR, 97214, USA

    Jihperng Jim Leu

  3. Taiwan Semiconductor Manufacturing Co. (TSMC), No. 9, Creation Road 1 Science-Based Ind. Park, Hsin-chu, Taiwan

    Wei William Lee

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Endo, K., Kishimoto, K., Matsubara, Y., Koyanagi, K. (2003). Plasma-Enhanced Chemical Vapor Deposition of FSG and a-C:F Low-k Materials. In: Ho, P.S., Leu, J.J., Lee, W.W. (eds) Low Dielectric Constant Materials for IC Applications. Springer Series in Advanced Microelectronics, vol 9. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-55908-2_5

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  • DOI: https://doi.org/10.1007/978-3-642-55908-2_5

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