Abstract
In this paper, an efficient method to relax timing requirements of CRFF sigma-delta modulators has been proposed. A system optimization to circuit level design was finished. Class-C inverter was used to realize half delay integrators of the proposed structure. A 4th-order 1-bit CRFF topology was implemented in smic 0.13μm CMOS technology. With 31.25MHz sampling frequency and 64x oversampling ratio, 13.2-bit resolution has been reached. The whole circuit consumes 472.63-μW power from a single 0.6V supply voltage. Thus, a low-voltage low-power medium-bandwidth high-accuracy sigma-delta modulator has been obtained.
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Li, H., Wang, Y., Jia, S., Zhang, X. (2011). Effective Design for CRFF Sigma-Delta Modulators Using Inverters Based on 0.13μm CMOS. In: Lee, J. (eds) Advanced Electrical and Electronics Engineering. Lecture Notes in Electrical Engineering, vol 87. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19712-3_72
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DOI: https://doi.org/10.1007/978-3-642-19712-3_72
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19711-6
Online ISBN: 978-3-642-19712-3
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