Abstract
A continuous-time low-pass sigma-delta modulator (ΣΔM) with a chain of integrators with weighted capacitive feedforward (CICFF) summation topology is fabricated by TSMC 0.18-μm CMOS process. The summation of feedforward signals is implemented by the weighted capacitors without the necessity of any additional active components. The quantizer uses a 1-bit comparator which may achieve high linearity easily. Under 1.8-V supply voltage, the measured results achieve a dynamic range of 52 dB over a 5-MHz signal bandwidth, a peak SNDR of 53.37 dB, an ENOB of 8.53 bits, an IM3 of −56 dB, and a power dissipation of 11.8 mW. With the pads included, the chip area is 0.35 (0.563 × 0.636) mm2.
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Acknowledgments
The authors would like to appreciate the staff of CIC for their technical supports and greatly appreciate Professor Ron-Yi Liu for his valuable discussion.
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© 2015 Springer International Publishing Switzerland
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Huang, JF., Wen, JY., Chen, WC. (2015). Chip Design of a Continuous-Time 5-MHz Low-Pass Sigma-Delta Modulator. In: Wong, W. (eds) Proceedings of the 4th International Conference on Computer Engineering and Networks. Lecture Notes in Electrical Engineering, vol 355. Springer, Cham. https://doi.org/10.1007/978-3-319-11104-9_106
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DOI: https://doi.org/10.1007/978-3-319-11104-9_106
Publisher Name: Springer, Cham
Print ISBN: 978-3-319-11103-2
Online ISBN: 978-3-319-11104-9
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