Abstract
This chapter describes the low power memory cell design technique. Section 4.1 introduces fundamentals of leakage of SRAM array. In Sect. 4.2, source line voltage control techniques are explained as new designs to reduce standby power dissipation. Using the techniques for a 16-Mbit SRAM chip fabricated in 0. 13-μm CMOS technology, the cell-standby current is 16.7 fA at 25 ∘ C and 101.7 fA at 90 ∘ C. By applying the techniques to 1-Mbit 130-nm embedded SRAM, the leakage current is reduced by about 90% from 230 to 25 μA. In Sect. 4.3, a new SRAM cell layout design developed for low-voltage operation is described. A lithographically symmetrical cell for lower-voltage operation was developed. The measured butterfly curves indicate that the memory cell has a large enough noise margin even at 0.3 V.
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Osada, K., Yamaoka, M. (2011). Low Power Memory Cell Design Technique. In: Ishibashi, K., Osada, K. (eds) Low Power and Reliable SRAM Memory Cell and Array Design. Springer Series in Advanced Microelectronics, vol 31. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19568-6_4
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DOI: https://doi.org/10.1007/978-3-642-19568-6_4
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