Low Power and Reliable SRAM Memory Cell and Array Design

  • Koichiro Ishibashi
  • Kenichi Osada

Part of the Springer Series in Advanced Microelectronics book series (MICROELECTR., volume 31)

Table of contents

  1. Front Matter
    Pages i-xi
  2. Koichiro Ishibashi
    Pages 1-4
  3. Kenichi Osada
    Pages 5-10
  4. Masanao Yamaoka, Yasumasa Tsukamoto
    Pages 11-24
  5. Kenichi Osada, Masanao Yamaoka
    Pages 25-41
  6. Koji Nii, Masanao Yamaoka, Kenichi Osada
    Pages 43-88
  7. Koji Nii, Masanao Yamaoka
    Pages 125-138
  8. Back Matter
    Pages 139-143

About this book

Introduction

Success in the development of recent advanced semiconductor device technologies is due to the success of SRAM memory cells. This book addresses various issues for designing SRAM memory cells for advanced CMOS technology. To study LSI design, SRAM cell design is the best materials subject because issues about variability, leakage and reliability have to be taken into account for the design.

Keywords

CMOS LSI Memory cell Reliability SRAM Study

Editors and affiliations

  • Koichiro Ishibashi
    • 1
  • Kenichi Osada
    • 2
  1. 1.The University of Electro-CommunicationsTokyoJapan
  2. 2.Hitachi Ltd.Kokubunji-shi, TokyoJapan

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-642-19568-6
  • Copyright Information Springer-Verlag Berlin Heidelberg 2011
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Engineering
  • Print ISBN 978-3-642-19567-9
  • Online ISBN 978-3-642-19568-6
  • Series Print ISSN 1437-0387
  • About this book