Abstract
In SRAM, read and write are fundamental operations. To ensure the correct operations, the stability analysis is indispensable. In this chapter, electrical stability analysis is explained. In Sect. 3.1, the SRAM operations, read and write, are explained. In this section, the read stability, static-noise margin SNM, and the write stability are described. In SRAM design, V th variation of transistors has critical influence on SRAM operation. In Sect. 3.2, the V th variation of MOSFETs and its effect to SRAM are described. The V th variations can be divided into local and global components. In this section, the effect of V th variation is made visible using V th window curve analysis. In Sect. 3.3, by means of the conventional SNM and write margin analysis on the SRAM cell characteristics, expanded mathematical analysis to obtain the V th curve is described. The analysis is instructive to see stable V th conditions visually to achieve high-yield SRAM. Furthermore, the proposed analysis referred to as the worst-vector method allows to derive the minimum operation voltage of the SRAM Macros (V ddmin).
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
M.J. Pelgrom, A.C.J. Duinmaijar, Matching properties of MOS transistors. IEEE. J. Solid-State Circuits 24(5), 1433–1440 (1989)
M. Yamaoka et. al., Low power SRAM menu for SOC application using Yin-Yang-feedback memory cell, in Proceedings of 2004 Symposium on VLSI Circuits, pp. 288–291
Y. Tsukamoto, K. Nii, S. Imaoka, Y. Oda, S. Ohbayashi, T. Yoshizawa, H. Makino, K. Ishibashi, H. Shinohara, Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability, in Proceedings of ICCAD, Nov. 2005, pp. 394–405
F. Tachibana, T. Hiramoto, Re-examination of impact of intrinsic dopant fluctuations for ultra-small bulk and SOI CMOS, IEEE Trans. Electron Devices 48(9), 1995–2001 (2001)
P.A. Stolk, F.P. Widdershoven, D.B.M. Klaassen, Modeling statistical dopant fluctuations in mos transistors IEEE Trans. Electron Devices 45(9), 960–1971 (1998)
S. Ohbayashi et al., A 65 nm SoC embedded 6T-SRAM design for manufacturing with read and write cell stabilizing circuits, in Proceedings of 2006 Symposium on VLSI Circuits, 2006, pp. 17-18
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Yamaoka, M., Tsukamoto, Y. (2011). Electrical Stability (Read and Write Operations). In: Ishibashi, K., Osada, K. (eds) Low Power and Reliable SRAM Memory Cell and Array Design. Springer Series in Advanced Microelectronics, vol 31. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-19568-6_3
Download citation
DOI: https://doi.org/10.1007/978-3-642-19568-6_3
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-19567-9
Online ISBN: 978-3-642-19568-6
eBook Packages: EngineeringEngineering (R0)