Abstract
Network-on-Chip (NoC) is viewed as a viable substitution for traditional interconnection networks to achieve high performance, communication efficiency and reliability in complex VLSI architectures at deep sub micron. Achieving high performance, power efficiency with optimum area is a target for any routing algorithm in NoC. In this paper, we propose a novel routing scheme named ‘ERA’, which offers higher throughput with controlled delays while remaining power aware. ERA is an adaptive routing algorithm, which avoids congestion and tends to minimize the hot spots in the network. Unlike other existing algorithms, the proposed algorithm does not require any virtual channels to avoid deadlocks. We compare our algorithm with XY and OE on the basis of a performance metric called ‘power performance factor’ for different traffic patterns and injection models. Our results show that ERA performs better than these two algorithms.
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Dally, W.J., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Annual Design Automation Conference, Las Vegas, Nevada, United States, pp. 684–689. ACM, New York (2001)
Hu, J., Marculescu, R.: Dyad smart routing for network-on-chip. In: 41st Design Automation Conference (2004)
Chiu, G.-M.: The odd-even turn model for adaptive routing. IEEE Transactions on Parallel and Distributed Systems, 729–738 (2000)
Glass, C., Ni, L.: The turn model for adaptive routing. In: 19th Annual International Symposium, Computer Architecture, pp. 278–287 (1992)
Jain, L., Al-Hashimi, B., Gaur, M.S., Laxmi, V., Narayanan, A.: Nirgam: A simulator for noc interconnect routing and application modelling. In: Design Automation and Test in Europe (DATE), Nice, France (2007)
Wang, S., Zhu, X., Peh, L., Malik, S.: Orion: A power-performance simulator for interconnection networks. In: 35th annual ACM/IEEE International Symposium on Micro architecture, Istanbul, Turkey (2002)
Kahng, A.B., Li, B., Peh, L.S., Samadi, K.: Orion 2.0: A fast and accurate noc power and area model for early-stage design space exploration. In: Design Automation and Test in Europe (DATE), Nice, France (2009)
Cho, M.H., Lis, M., Shim, K.S., Kinsy, M., Devadas, S.: Path-based, randomized, oblivious, minimal routing. In: 2nd International Workshop on Network on Chip Architectures, New York (2009)
Rameshan, N., Biyani, A., Gaur, M., Laxmi, V., Ahmed, M.: Qos aware minimally adaptive xy routing for noc. In: 17th International Conference on Advanced Computing and Communication (ADCOM), Bangalore, India (2009)
Glass, C., Ni, L.: Adaptive routing in mesh-connected networks. In: 12th international conference on Distributed Computing Systems (1992)
Marvasti, M.B., Daneshtalab, M., Afzali-Kusha, A., Mohammadi, S.: Pampr: Power-aware and minimum path routing algorithm for nocs. In: International Conference on Electronics, Circuits and Systems, ICECS (2008)
Duato, J., Yalamanchili, S., Ni, L.: Interconnection Networks-An Engineering Approach. Morgan Kaufmann, San Francisco (2003)
Dally, W.J., Towles, B.: Principles and Practices of Interconnection Networks. Morgan Kaufmann, San Francisco (2003)
Varatkar, G.V., Marculescu, R.: On-chip traffic modeling and synthesis for MPEG-2 video applications. IEEE Transactions on Very Large Scale Integrated Systems 12, 108–119 (2004)
Soteriou, V., Wang, H., Peh, L.: A statistical traffic model for on-chip interconnection networks. In: IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS), pp. 104–116 (2006)
Paxson, V.: Fast, approximate synthesis of fractional gaussian noise for generating self-similar network traffic. Computer Communications Review 27(5), 5–18 (1997)
Rahmani, A.M., Afzali-Kusha, A., Pedram, M.: A novel synthetic traffic pattern for power/performance analysis of network-on-chips using negative exponential distribution. Journal of Low Power Electronics 5, 1–10 (2009)
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Sharma, V., Agarwal, R., Gaur, M.S., Laxmi, V., V., V. (2010). ERA: An Efficient Routing Algorithm for Power, Throughput and Latency in Network-on-Chips. In: Ding, C., Shao, Z., Zheng, R. (eds) Network and Parallel Computing. NPC 2010. Lecture Notes in Computer Science, vol 6289. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15672-4_41
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DOI: https://doi.org/10.1007/978-3-642-15672-4_41
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