Abstract
We propose a technique to efficiently partition a FSMD (Finite State Machine with Datapath) using a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. We develop a framework to estimate the potential power savings from partitioning. Using several sample circuits, the estimation framework shows that when the original machine is partitioned into two submachines, on average, 32% static power savings and 19% dynamic power savings can be expected, with a performance impact of 2%. The power savings with more than two partitions can be even higher, with a larger performance impact.
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Agarwal, N., Dimopoulos, N.J. (2009). Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing. In: Bertels, K., Dimopoulos, N., Silvano, C., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2009. Lecture Notes in Computer Science, vol 5657. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03138-0_12
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DOI: https://doi.org/10.1007/978-3-642-03138-0_12
Publisher Name: Springer, Berlin, Heidelberg
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