Abstract
This paper explores the potential of smart enumeration: enumeration of a design space giving the effect of exhaustive search, while using heuristics to order and reduce the search space. We characterise smart enumeration as having several key properties, including carefully chosen problem domains and techniques to speed up the search, such as those that exploit symmetry. We also generate reconfigurable hardware to accelerate part of the search. Our approach has been applied to technology mapping for field-programmable gate arrays, optimising area and power consumption.
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Todman, T., Fu, H., Tsoi, B., Mencer, O., Luk, W. (2009). Smart Enumeration: A Systematic Approach to Exhaustive Search. In: Svensson, L., Monteiro, J. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2008. Lecture Notes in Computer Science, vol 5349. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-95948-9_43
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DOI: https://doi.org/10.1007/978-3-540-95948-9_43
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