Nanoanalytical investigation of the dielectric gate stack for the realisation of III–V MOSFET devices

Abstract

Planar Si MOSFET technology using Si(ON) is rapidly approaching its theoretical limit and the search for new material is essential. n-type GaAs has a mobility 5 times higher than Si [1]. This makes it a suitable candidate for MOSFETs devices. So far, GaAs has not been used for practical MOSFETs because of the difficulties of making a good dielectric oxide layer in terms of leakage current and unpinned Fermi Level. Using processes pioneered by Passlack et al. [2], dielectric gate stacks consisting of a template layer of amorphous Ga₂O₃ followed by amorphous GdGaO have been grown on GaAs substrates. Careful deposition of Ga₂O₃ can leave the Fermi Level unpinned. The introduction of Gd is important in order to decrease the leakage of current.