Power and Timing Driven Physical Design Automation

Abstract

The paper presents why power and timing can be improved by physical design automation where the cells are generated on the fly. The non-use of cell libraries allows the implementation of any logic function defined at logic synthesis, using simple gates or static CMOS complex gates – SCCG. The use of SCCG reduces the amount of transistor and helps to reduce wire length. It is discussed the main strategies in the automatic layout synthesis, like transistor topology, contacts and vias management, body ties placement, power lines management, routing management and transistor sizing. In both methodologies, standard cell and automatic layout, it is needed accurate pre-characterization tools. The development of efficient physical design automation is the key to find better solution than traditional standard cell methodologies.